PIC17C756A-16E/L Microchip Technology, PIC17C756A-16E/L Datasheet - Page 289
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PIC17C756A-16E/L
Manufacturer Part Number
PIC17C756A-16E/L
Description
IC MCU CMOS 16MHZ 16K EPRM68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-16E/L
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
68-PLCC
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-16E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
INDEX
A
A/D
A/D Interrupt........................................................................ 38
A/D Interrupt Flag bit, ADIF................................................. 38
A/D Module Interrupt Enable, ADIE .................................... 36
ACK................................................................................... 144
Acknowledge Data bit, AKD .............................................. 136
Acknowledge Pulse........................................................... 144
Acknowledge Sequence Enable bit, AKE ......................... 136
Acknowledge Status bit, AKS ........................................... 136
ADCON0 ............................................................................. 49
ADCON1 ............................................................................. 49
ADDLW ............................................................................. 202
ADDWF ............................................................................. 202
ADDWFC .......................................................................... 203
ADIE.................................................................................... 36
ADIF .................................................................................... 38
ADRES Register ............................................................... 179
ADRESH ............................................................................. 49
ADRESL.............................................................................. 49
AKD................................................................................... 136
AKE ................................................................................... 136
AKS ........................................................................... 136, 159
ALU ..................................................................................... 11
ALUSTA ............................................................................ 198
ALUSTA Register................................................................ 51
ANDLW ............................................................................. 203
ANDWF ............................................................................. 204
Application Note AN552, ’Implementing Wake-up
on Keystroke.’ ..................................................................... 74
Application Note AN578, "Use of the SSP Module
in the I
Assembler
Asynchronous Master Transmission ................................. 123
Asynchronous Transmitter ................................................ 123
2000 Microchip Technology Inc.
Accuracy/Error .......................................................... 189
ADCON0 Register..................................................... 179
ADCON1 Register..................................................... 180
ADIF bit ..................................................................... 181
Analog Input Model Block Diagram........................... 184
Analog-to-Digital Converter....................................... 179
Block Diagram........................................................... 181
Configuring Analog Port Pins.................................... 186
Configuring the Interrupt ........................................... 181
Configuring the Module............................................. 181
Connection Considerations....................................... 189
Conversion Clock...................................................... 185
Conversions .............................................................. 186
Converter Characteristics ......................................... 263
Delays ....................................................................... 183
Effects of a RESET ................................................... 188
Equations .................................................................. 183
Flow Chart of A/D Operation..................................... 187
GO/DONE bit ............................................................ 181
Internal Sampling Switch (Rss) Impedence .............. 183
Operation During SLEEP .......................................... 188
Sampling Requirements............................................ 183
Sampling Time .......................................................... 183
Source Impedence.................................................... 183
Time Delays .............................................................. 183
Transfer Function...................................................... 189
MPASM Assembler................................................... 233
2
C Multi-Master Environment."............................... 143
B
Bank Select Register (BSR) ............................................... 57
Banking......................................................................... 46, 57
Baud Rate Formula........................................................... 120
Baud Rate Generator ....................................................... 153
Baud Rate Generator (BRG) ............................................ 120
Baud Rates
BCF .................................................................................. 204
BCLIE ................................................................................. 36
BCLIF ................................................................................. 38
BF ............................................................. 134, 144, 159, 162
Bit Manipulation ................................................................ 198
Block Diagrams
BODEN ............................................................................... 31
Borrow ................................................................................ 11
BRG .......................................................................... 120, 153
Brown-out Protection .......................................................... 31
Brown-out Reset (BOR)...................................................... 31
BSF................................................................................... 205
BSR .................................................................................... 57
BSR Operation ................................................................... 57
BTFSC .............................................................................. 205
BTFSS .............................................................................. 206
BTG .................................................................................. 206
Buffer Full bit, BF .............................................................. 144
Buffer Full Status bit, BF................................................... 134
Bus Arbitration .................................................................. 170
Bus Collision
Asynchronous Mode................................................. 122
Synchronous Mode................................................... 121
A/D............................................................................ 181
Analog Input Model................................................... 184
Baud Rate Generator ............................................... 153
BSR Operation ........................................................... 57
External Brown-out Protection Circuit (Case1)........... 31
External Power-on Reset Circuit ................................ 24
External Program Memory Connection ...................... 45
I
I
Indirect Addressing..................................................... 54
On-chip Reset Circuit ................................................. 23
PORTD ....................................................................... 80
PORTE ........................................................... 82, 90, 91
Program Counter Operation ....................................... 56
PWM......................................................................... 107
RA0 and RA1.............................................................. 72
RA2............................................................................. 72
RA3............................................................................. 73
RA4 and RA5.............................................................. 73
RB3:RB2 Port Pins ..................................................... 75
RB7:RB4 and RB1:RB0 Port Pins .............................. 74
RC7:RC0 Port Pins..................................................... 78
SSP (I
SSP (SPI Mode) ....................................................... 137
SSP Module (I
SSP Module (I
SSP Module (SPI Mode) .......................................... 133
Timer3 with One Capture and One Period Register. 110
TMR1 and TMR2 in 16-bit Timer/Counter Mode ...... 105
TMR1 and TMR2 in Two 8-bit Timer/Counter Mode 104
TMR3 with Two Capture Registers........................... 112
Using CALL, GOTO.................................................... 56
WDT ......................................................................... 193
Section...................................................................... 170
2
2
C Master Mode ...................................................... 151
C Module................................................................ 143
2
C Mode)........................................................ 143
2
2
C Master Mode) ............................... 133
C Slave Mode) ................................. 133
PIC17C7XX
DS30289B-page 289