PIC17C766-16E/PT Microchip Technology, PIC17C766-16E/PT Datasheet - Page 221
PIC17C766-16E/PT
Manufacturer Part Number
PIC17C766-16E/PT
Description
IC MCU CMOS 16MHZ 16K EPRM80TQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C766-16E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C766-16E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2000 Microchip Technology Inc.
After Interrupt
operation
Decode
PC
GLINTD =
Q1
No
=
operation
operation
Return from Interrupt
[ label ]
None
TOS
0
PCLATH is unchanged.
GLINTD
Return from Interrupt. Stack is POP’ed
and Top-of-Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
1
2
RETFIE
0000
Q2
No
No
TOS
0
GLINTD;
(PC);
RETFIE
0000
operation
GLINTD
Clear
Q3
No
0000
from stack
operation
POP PC
Q4
No
0101
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
operation
Decode
WREG
WREG
Q1
No
=
=
operation
Return Literal to WREG
[ label ]
0
k
PCLATH is unchanged
None
WREG is loaded with the eight-bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
1
2
TABLE
literal 'k'
Read
1011
Q2
No
CALL TABLE ; WREG contains table
:
ADDWF PC
RETLW k0
RETLW k1
:
:
RETLW kn
0x07
value of k7
k
(WREG); TOS
PIC17C7XX
255
RETLW k
0110
operation
Process
;
;
;
; WREG = offset
; Begin table
;
; End of table
Data
Q3
No
DS30289B-page 221
offset value
WREG now has
table value
kkkk
(PC);
from stack,
operation
POP PC
Write to
WREG
Q4
No
kkkk
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