ATMEGA16-16AC Atmel, ATMEGA16-16AC Datasheet - Page 18
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ATMEGA16-16AC
Manufacturer Part Number
ATMEGA16-16AC
Description
IC AVR MCU 16K 16MHZ COM 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16-16AC
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Manufacturer
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Price
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Data Memory Access
Times
EEPROM Data
Memory
EEPROM Read/Write
Access
2466T–AVR–07/10
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 10. On-chip Data SRAM Access Cycles
The ATmega16 contains 512 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
For a detailed description of SPI, JTAG, and Parallel data downloading to the EEPROM, see
page
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used. See
ing EEPROM Corruption” on page 22
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
273,
page
Address
clk
Data
Data
278, and
WR
CPU
RD
page
Compute Address
262, respectively.
T1
Memory Access Instruction
for details on how to avoid problems in these situations.
Address Valid
CPU
Table
T2
cycles as described in
1. A self-timing function, however, lets
Next Instruction
T3
ATmega16(L)
Figure
10.
“Prevent-
18
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