ATMEGA8515-16AC Atmel, ATMEGA8515-16AC Datasheet - Page 8
ATMEGA8515-16AC
Manufacturer Part Number
ATMEGA8515-16AC
Description
IC AVR MCU 8K 16MHZ COM 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8515-16AC
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8515-16AC
Manufacturer:
MOT
Quantity:
3 450
Part Number:
ATMEGA8515-16AC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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AVR CPU Core
Introduction
Architectural Overview
8
ATmega8515(L)
This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals, and handle interrupts.
Figure 3. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the Program
memory are executed with a single level pipelining. While one instruction is being exe-
cuted, the next instruction is pre-fetched from the Program memory. This concept
enables instructions to be executed in every clock cycle. The Program memory is In-
System re programmable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Control Lines
Instruction
Instruction
Program
Memory
Register
Decoder
Flash
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
I/O Module 2
Comparator
I/O Module1
I/O Module n
2512K–AVR–01/10
Watchdog
Interrupt
Timer
Analog
Unit
Unit
SPI
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