ATMEGA8535L-8PC Atmel, ATMEGA8535L-8PC Datasheet - Page 251
![IC AVR MCU 8K LV 8MHZ COM 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8535L-8PC
Manufacturer Part Number
ATMEGA8535L-8PC
Description
IC AVR MCU 8K LV 8MHZ COM 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535L-8PC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Serial Programming Pin
Mapping
2502K–AVR–10/06
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input), and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 107 on page 251, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface.
Table 107. Pin Mapping Serial Programming
Figure 124. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the Serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
High:> 2 CPU clock cycles for f
Symbol
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock
2. VCC - 0.3 < AVCC < VCC + 0.3. However, AVCC should always be within 2.7 - 5.5V.
MOSI
MISO
SCK
source to the XTAL1 pin.
MOSI
MISO
SCK
Pins
PB5
PB6
PB7
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
PB5
PB6
PB7
XTAL1
RESET
GND
I/O
(1)
O
I
I
AVCC
VCC
Description
Serial Data in
Serial Data out
Serial Clock
ATmega8535(L)
2.7 - 5.5V
2.7 - 5.5V
(2)
ck
ck
≥ 12 MHz
≥ 12 MHz
251
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