ATMEGA8515L-8PC Atmel, ATMEGA8515L-8PC Datasheet
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ATMEGA8515L-8PC
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ATMEGA8515L-8PC Summary of contents
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... PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega8515L – 4.5 - 5.5V for ATmega8515 • Speed Grades – MHz for ATmega8515L – MHz for ATmega8515 ® 8-bit Microcontroller 8-bit Microcontroller with 8K Bytes ...
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Pin Configurations Figure 1. Pinout ATmega8515 TQFP/MLF (MOSI) PB5 1 (MISO) PB6 2 (SCK) PB7 3 RESET 4 (RXD) PD0 5 NC* 6 (TXD) PD1 7 (INT0) PD2 8 (INT1) PD3 9 (XCK) PD4 10 (OC1A) PD5 11 ATmega8515(L) 2 ...
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Overview Block Diagram 2512K–AVR–01/10 The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the sys- ...
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... Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications ...
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Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E(PE2..PE0) RESET XTAL1 XTAL2 2512K–AVR–01/10 Digital supply voltage. Ground. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for ...
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... Resources ATmega8515( comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr. 2512K–AVR–01/10 ...
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About Code Examples 2512K–AVR–01/10 This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all ...
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AVR CPU Core Introduction Architectural Overview ATmega8515(L) 8 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform ...
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ALU – Arithmetic Logic Unit 2512K–AVR–01/10 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used ...
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Status Register ATmega8515(L) 10 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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General Purpose Register File 2512K–AVR–01/10 The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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The X-register, Y-register, and Z-register Stack Pointer ATmega8515(L) 12 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, ...
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Instruction Execution Timing Reset and Interrupt Handling 2512K–AVR–01/10 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. Figure ...
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ATmega8515(L) 14 also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 166. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and ...
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Interrupt Response Time 2512K–AVR–01/10 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set global interrupt enable sleep; enter sleep, ...
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AVR ATmega8515 Memories In-System Reprogrammable Flash Program memory ATmega8515(L) 16 This section describes the different memories in the ATmega8515. The AVR architec- ture has two main memory spaces, the Data Memory and the Program memory space. In addition, the ATmega8515 ...
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SRAM Data Memory 2512K–AVR–01/10 Figure 9 shows how the ATmega8515 SRAM Memory is organized. The lower 608 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File ...
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Data Memory Access Times ATmega8515(L) 18 Figure 9. Data Memory Map Data Memory 32 Registers 64 I/O Registers Internal SRAM (512 x 8) External SRAM (0 - 64K x 8) This section describes the general access timing concepts for internal ...
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EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register – EEARH and EEARL 2512K–AVR–01/10 The ATmega8515 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and ...
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The EEPROM Data Register – EEDR The EEPROM Control Register – EECR ATmega8515(L) 20 Bit MSB Read/Write R/W R/W R/W Initial Value • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, ...
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Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR ...
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ATmega8515(L) 22 Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ...
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EEPROM Write During Power- down Sleep Mode 2512K–AVR–01/10 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly ...
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Preventing EEPROM Corruption I/O Memory ATmega8515(L) 24 During periods of low V , the EEPROM data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly. These issues are ...
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External Memory Interface Overview Using the External Memory Interface 2512K–AVR–01/10 With all the features the External Memory Interface provides well suited to operate as an interface to memory devices such as external SRAM and Flash, and peripherals such ...
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Address Latch Requirements ATmega8515(L) 26 The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special Function IO Register – SFIOR. When ...
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Pull-up and Bus Keeper Timing 2512K–AVR–01/10 The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port Register is written to one. To reduce power consumption in sleep mode recom- mended to disable the pull-ups ...
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ATmega8515(L) 28 Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 T1 System Clock (CLK ) CPU ALE A15:8 Prev. Addr. DA7:0 Prev. Data Address WR DA7:0 (XMBK = 0) Prev. Data Address DA7:0 (XMBK ...
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XMEM Register Description MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR 2512K–AVR–01/10 Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = System Clock (CLK ) CPU ALE A15:8 Prev. Addr. ...
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ATmega8515(L) 30 SRAM address space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits. Table 2. Sector Limits with Different Settings of SRL2..0 SRL2 SRL1 SRL0 ...
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Special Function IO Register – SFIOR Using all Locations of External Memory Smaller than 64 KB 2512K–AVR–01/10 Bit – XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 6 – XMBK: External Memory ...
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ATmega8515(L) 32 Figure 17. Address Map with 32 KB External Memory Memory Configuration AVR Memory Map 0x0000 Internal Memory 0x025F 0x0260 External 0x7FFF 0x8000 Memory 0x825F 0x8260 (Unused) 0xFFFF External 32K SRAM 0x0000 0x025F 0x0260 0x7FFF 2512K–AVR–01/10 ...
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Using all 64KB Locations of External Memory 2512K–AVR–01/10 Since the External Memory is mapped after the Internal Memory as shown in Figure 11, only 64,928 bytes of External Memory is available by default (address space 0x0000 to 0x025F is reserved ...
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System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clk CPU I/O Clock – clk I/O ATmega8515(L) 34 Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks need ...
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Flash Clock – clk FLASH Clock Sources Default Clock Source Crystal Oscillator 2512K–AVR–01/10 The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. The device has the following clock source ...
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ATmega8515( use, the amount of stray capacitance, and the electromagnetic noise of the environ- ment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 7. For ceramic resonators, the capacitor values given by ...
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Low-frequency Crystal Oscillator 2512K–AVR–01/10 Table 8. Start-up Times for the Crystal Oscillator Clock Selection (Continued) Start-up Time CKSEL0 SUT1..0 from Power-down 1 01 16K 16K 16K CK Notes: 1. These options should only be ...
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External RC Oscillator ATmega8515(L) 38 For timing insensitive applications, the external RC configuration shown in Figure 20 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming ...
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... MHz Oscillator frequency selected, this calibration gives a frequency within ± the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accu- racy at any given V and Temperature. When this Oscillator is used as the chip clock, ...
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External Clock ATmega8515(L) 40 will increase the frequency of the internal Oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do ...
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Power Management and Sleep Modes MCU Control Register – MCUCR MCU Control and Status Register – MCUCSR 2512K–AVR–01/10 Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes ...
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Extended MCU Control Register – EMCUCR Idle Mode Power-down Mode ATmega8515(L) 42 Bit SM0 SRL2 SRL1 Read/Write R/W R/W R/W Initial Value • Bits 7 – SM0: Sleep Mode Select Bit 0 The Sleep ...
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Standby Mode Minimizing Power Consumption Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer 2512K–AVR–01/10 When the SM2..0 bits are written to 110, and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. ...
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Port Pins ATmega8515(L) 44 When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clk ...
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System Control and Reset Resetting the AVR Reset Sources 2512K–AVR–01/10 During Reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must be ...
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... V production test. This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega8515L and BODLEVEL=0 for ATmega8515. BODLEVEL=1 is not applicable for ATmega8515. DATA BUS ...
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Power-on Reset 2512K–AVR–01/10 A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 18. The POR is activated whenever V detection level. The POR circuit can be used to trigger ...
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External Reset Brown-out Detection ATmega8515( External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 18) will generate a reset, even if the clock is not ...
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Watchdog Reset MCU Control and Status Register – MCUCSR 2512K–AVR–01/10 When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting ...
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Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer ATmega8515(L) 50 ATmega8515 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator. ...
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Watchdog Timer Control Register – WDTCR 2512K–AVR–01/10 Table 20. WDT Configuration as a Function of the Fuse Settings of S8515C and WDTON. S8515C WDTON Unprogrammed Unprogrammed Unprogrammed Programmed Programmed Unprogrammed Programmed Programmed Figure 28. Watchdog Timer WATCHDOG OSCILLATOR Bit 7 ...
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ATmega8515( the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four ...
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Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 2512K–AVR–01/10 The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level. This ...
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Interrupts Interrupt Vectors in ATmega8515 ATmega8515(L) 54 This section describes the specifics of the interrupt handling as performed in ATmega8515. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Table 22. ...
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Table 23. Reset and Interrupt Vectors Placement BOOTRST IVSEL Reset Address 1 0 $0000 1 1 $0000 0 0 Boot Reset Address 0 1 Boot Reset Address Note: 1. The Boot Reset Address is shown in Table 78 on ...
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ATmega8515(L) 56 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the ...
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Moving Interrupts between Application and Boot Space General Interrupt Control Register – GICR 2512K–AVR–01/10 $C12 out SPH,r16 $C13 ldi r16,low(RAMEND) $C14 out SPL,r16 $C15 sei $C16 <instr> The General Interrupt Control Register controls the placement of the Interrupt Vector table. ...
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ATmega8515(L) 58 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when ...
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I/O Ports Introduction 2512K–AVR–01/10 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin ...
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Ports as General Digital I/O Configuring the Pin ATmega8515(L) 60 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 30. General Digital I/O ...
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Reading the Pin Value 2512K–AVR–01/10 enabled state is fully acceptable high-impedant environment will not notice the dif- ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR ...
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ATmega8515(L) 62 signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in ...
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Digital Input Enable and Sleep Modes 2512K–AVR–01/10 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned ...
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Unconnected pins Alternate Port Functions ATmega8515( some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described ...
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Table 25 summarizes the function of the overriding signals. The pin and port indexes from Figure 33 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table ...
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Special Function IO Register – SFIOR Alternate Functions of Port A ATmega8515(L) 66 Bit – XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is ...
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Alternate Functions Of Port B 2512K–AVR–01/10 Table 28. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/AD3 PA2/AD2 PUOE SRE SRE PUOV ~(WR | ADA) • ~(WR | ADA) • PortA3 PortA2 DDOE SRE SRE DDOV WR | ADA ...
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ATmega8515(L) 68 • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of ...
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Table 30. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/SCK PB6/MISO PUOE SPE • MSTR SPE • MSTR PUOV PORTB7 • PUD PORTB6 • PUD DDOE SPE • MSTR SPE • MSTR DDOV 0 0 PVOE SPE ...
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Alternate Functions of Port C ATmega8515(L) 70 The Port C pins with alternate functions are shown in Table 32. Table 32. Port C Pins Alternate Functions Port Pin Alternate Function PC7 A15 (External memory interface address bit 15) PC6 A14 ...
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Table 33. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PC7/A15 PUOE SRE • (XMM<1) PUOV 0 DDOE SRE • (XMM<1) DDOV 1 PVOE SRE • (XMM<1) PVOV A15 DIEOE 0 DIEOV 0 DI – AIO – Table ...
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Alternate Functions of Port D ATmega8515(L) 72 The Port D pins with alternate functions are shown in Table 35. Table 35. Port D Pins Alternate Functions Port Pin Alternate Function PD7 RD (Read Strobe to External Memory) PD6 WR (Write ...
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Table 36 and Table 37 relate the alternate functions of Port D to the overriding signals shown in Figure 33 on page 64. Table 36. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/RD PD6/WR PUOE SRE SRE PUOV ...
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Alternate Functions of Port E ATmega8515(L) 74 The Port E pins with alternate functions are shown in Table 38. Table 38. Port E Pins Alternate Functions Port Pin Alternate Function PE2 OC1B (Timer/Counter1 Output Compare B Match Output) PE1 ALE ...
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Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B ...
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Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE ...
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External Interrupts MCU Control Register – MCUCR 2512K–AVR–01/10 The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides ...
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Extended MCU Control Register – EMCUCR General Interrupt Control Register – GICR ATmega8515(L) 78 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges ...
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General Interrupt Flag Register – GIFR 2512K–AVR–01/10 corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Inter- rupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and ...
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Timer/Counter0 with PWM Overview Registers ATmega8515(L) 80 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width ...
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Definitions Timer/Counter Clock Sources Counter Unit 2512K–AVR–01/10 inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk T0 The double buffered Output Compare Register (OCR0) is compared with ...
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Output Compare Unit ATmega8515(L) 82 clk Timer/Counter clock, referred to as clk Tn top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is ...
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Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit 2512K–AVR–01/10 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) ...
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Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega8515(L) 84 The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera- tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare ...
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Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode 2512K–AVR–01/10 The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and ...
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Fast PWM Mode ATmega8515(L) 86 when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 ...
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Figure 39. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used ...
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Phase Correct PWM Mode ATmega8515(L) 88 The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly ...
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Timer/Counter Timing Diagrams 2512K–AVR–01/10 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The N variable represents the prescale factor (1, 8, ...
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ATmega8515(L) 90 Figure 42. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 43 shows the setting of OCF0 in all modes except CTC mode. Figure 43. Timer/Counter Timing Diagram, ...
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Timer/Counter Register Description Timer/Counter Control Register – TCCR0 2512K–AVR–01/10 Bit FOC0 WGM00 COM01 Read/Write W R/W R/W Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active ...
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ATmega8515(L) 92 When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 45 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode ...
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Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK 2512K–AVR–01/10 The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 48. Clock Select Bit Description CS02 CS01 CS00 ...
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Timer/Counter Interrupt Flag Register – TIFR ATmega8515(L) 94 When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a ...
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Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source 2512K–AVR–01/10 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The Timer/Counter ...
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Special Function IO Register – SFIOR ATmega8515(L) 96 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari- ation of the system clock ...
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Timer/Counter1 Overview 2512K–AVR–01/10 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., allows 16-bit PWM) • Two Independent Output Compare Units ...
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Registers ATmega8515(L) 98 Figure 47. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 29 on page 67, and Table 35 on page 72 ...
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Definitions Compatibility 2512K–AVR–01/10 also set the Compare Match Flag (OCF1A/B) which can be used to generate an output compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the ...
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Accessing 16-bit Registers ATmega8515(L) 100 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; Save ...
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Reusing the Temporary High Byte Register ATmega8515(L) 102 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ...
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Timer/Counter Clock Sources Counter Unit 2512K–AVR–01/10 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in ...
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Input Capture Unit ATmega8515(L) 104 how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 109. The Timer/Counter Overflow (TOV1) Flag is set ...
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Input Capture Trigger Source Noise Canceler Using the Input Capture Unit 2512K–AVR–01/10 byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can ...
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Output Compare Units ATmega8515(L) 106 measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x ...
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Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit 2512K–AVR–01/10 sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this ...
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Compare Match Output Unit ATmega8515(L) 108 The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control ...
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Compare Output Mode and Waveform Generation Modes of Operation Normal Mode 2512K–AVR–01/10 The Waveform Generator uses the COM1x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no ...
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Clear Timer on Compare Match (CTC) Mode ATmega8515(L) 110 In clear timer on compare or CTC mode (WGM13 12), the OCR1A or ICR1 Reg- ister are used to manipulate the counter resolution. In CTC mode the counter ...
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Fast PWM Mode 2512K–AVR–01/10 The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) pro- vides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by ...
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ATmega8515(L) 112 are enabled, the interrupt handler routine can be used for updating the TOP and com- pare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value ...
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Phase Correct PWM Mode 2512K–AVR–01/10 The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, ...
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ATmega8515(L) 114 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT- TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer ...
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Phase and Frequency Correct PWM Mode 2512K–AVR–01/10 The phase and frequency correct Pulse Width Modulation, or phase and frequency cor- rect PWM mode (WGM13 provides a high resolution phase and frequency correct PWM waveform generation option. ...
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ATmega8515(L) 116 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, ...
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Timer/Counter Timing Diagrams 2512K–AVR–01/10 The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register ...
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ATmega8515(L) 118 Figure 58. Timer/Counter Timing Diagram, No Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx ...
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Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A 2512K–AVR–01/10 Bit COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit ...
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ATmega8515(L) 120 Table 52. Compare Output Mode, Phase Correct and Phase and Frequency Correct (1) PWM COM1A1/ COM1A0/ COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected WGM13 11: Toggle OC1A on Compare Match, ...
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Table 53. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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Timer/Counter1 Control Register B – TCCR1B ATmega8515(L) 122 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the ...
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Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL 2512K–AVR–01/10 Bit Read/Write R/W R/W R/W Initial Value The two Timer/Counter ...
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Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega8515(L) 124 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value ...
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Timer/Counter Interrupt Flag (1) Register – TIFR 2512K–AVR–01/10 Bit TOV1 OCF1A OC1FB Read/Write R/W R/W R/W Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described ...
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Serial Peripheral Interface – SPI ATmega8515(L) 126 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8515 and peripheral devices or between several AVR devices. The ATmega8515 SPI includes the following features: • Full Duplex, 3-wire Synchronous ...
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When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register ...
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ATmega8515(L) 128 (1) Table 55. SPI Pin Overrides Pin Direction, Master SPI MISO Input SCK User Defined SS User Defined Note: 1. See “Alternate Functions Of Port B” on page 67 for a detailed description of how to define the ...
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SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait ...
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ATmega8515(L) 130 The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; ...
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SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR 2512K–AVR–01/10 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO ...
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ATmega8515(L) 132 be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is ...
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SPI Status Register – SPSR SPI Data Register – SPDR 2512K–AVR–01/10 Bit SPIF WCOL – Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is ...
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Data Modes ATmega8515(L) 134 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 62 and Figure 63. ...
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USART Single USART 2512K–AVR–01/10 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation ...
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ATmega8515(L) 136 Figure 64. USART Block Diagram UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: 1. Refer to Figure 1 on page 2, Table 37 on page 73, and Table 31 on ...
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AVR USART vs. AVR UART – Compatibility Clock Generation 2512K–AVR–01/10 The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver ...
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Internal Clock Generation – The Baud Rate Generator ATmega8515(L) 138 Signal description: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK ...
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Double Speed Operation (U2X) External Clock Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock 2512K–AVR–01/10 The transfer rate can be doubled by setting the U2X bit in UCSRA. ...
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Frame Formats Parity Bit Calculation ATmega8515(L) 140 A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations ...
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USART Initialization 2512K–AVR–01/10 If used, the parity bit is located between the last data bit and first stop bit of a serial frame. The USART has to be initialized before any communication can take place. The initial- ization process normally ...
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Data Transmission – The USART Transmitter Sending Frames with Data Bits ATmega8515(L) 142 More advanced initialization routines can be made that include frame format as parame- ters, disable interrupts and so on. However, many applications use a ...
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Sending Frames with 9 Data Bits Transmitter Flags and Interrupts 2512K–AVR–01/10 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written ...
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Parity Generator Disabling the Transmitter ATmega8515(L) 144 interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty Interrupt, otherwise a new ...
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Data Reception – The USART Receiver Receiving Frames with Data Bits Receiving Frames with 9 Data Bits 2512K–AVR–01/10 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When ...
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ATmega8515(L) 146 (1) Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get status and ninth bit, then data from buffer in r18, UCSRA in r17, UCSRB in r16, UDR ; If ...
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Receive Compete Flag and Interrupt Receiver Error Flags 2512K–AVR–01/10 The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one ...
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Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception ATmega8515(L) 148 The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is ...
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Asynchronous Clock Recovery Asynchronous Data Recovery 2512K–AVR–01/10 The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig- ure 68 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times ...
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Asynchronous Operational Range ATmega8515(L) 150 Figure 70 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 70. Stop Bit Sampling and Next Start Bit Sampling RxD Sample 1 ...
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Multi-processor Communication Mode 2512K–AVR–01/10 Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit) R (%) slow 5 93.20 6 94.12 7 94.81 8 95.36 9 95.81 10 96.17 Table 62. ...
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Using MPCM ATmega8515(L) 152 The Multi-processor Communication mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular Slave ...
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Accessing UBRRH/UCSRC Registers Write Access 2512K–AVR–01/10 The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. When doing a write access of this I/O location, the ...
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Read Access ATmega8515(L) 154 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any of these registers. The read access is controlled ...
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USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA 2512K–AVR–01/10 Bit Read/Write R/W R/W R/W Initial Value The USART Transmit Data Buffer Register and USART Receive ...
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USART Control and Status Register B – UCSRB ATmega8515(L) 156 This bit is set if the next character in the receive buffer had a Frame Error when received. For example, when the first stop bit of the next character in ...
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USART Control and Status Register C – UCSRC 2512K–AVR–01/10 Writing this bit to one enables the USART Transmitter. The Transmitter will override nor- mal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to ...
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ATmega8515(L) 158 Table 64. UPM Bits Settings UPM1 UPM0 • Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The ...
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USART Baud Rate Registers – UBRRL and UBRRH Examples of Baud Rate Setting 2512K–AVR–01/10 Bit URSEL – – Read/Write R R/W R/W R/W Initial Value The ...
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Table 68. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 ...
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Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k 15 ...
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Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k 68 ...
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Analog Comparator Analog Comparator Control and Status Register – ACSR ATmega8515(L) 164 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than ...
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Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana- log Comparator interrupt is activated. When written logic zero, the interrupt ...
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Boot Loader Support – Read-While-Write Self-Programming Features Application and Boot Loader Flash Sections Application Section BLS – Boot Loader Section Read-While-Write and No Read-While-Write Flash Sections ATmega8515(L) 166 The Boot Loader Support provides a real Read-While-Write Self-Programming mecha- nism for ...
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RWW – Read-While-Write Section NRWW – No Read-While-Write Section 2512K–AVR–01/10 Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write sec- tion” refers to ...
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Boot Loader Lock bits ATmega8515(L) 168 (1) Figure 73. Memory Sections Program Memory BOOTSZ = '11' $0000 Application Flash Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ ...
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Entering the Boot Loader Program 2512K–AVR–01/10 Table 74. Boot Lock Bit0 Protection Modes (Application Section) BLB0 Mode BLB02 BLB01 Note: 1. “1” means unprogrammed, “0” means programmed Table ...
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Store Program memory Control Register – SPMCR ATmega8515(L) 170 The Store Program memory Control Register contains the control bits needed to control the Boot Loader operations. Bit SPMIE RWWSB – Read/Write R Initial Value 0 ...
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Addressing the Flash During Self- Programming 2512K–AVR–01/10 the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase SPM instruction is executed within four clock cycles. The ...
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Self-Programming the Flash ATmega8515(L) 172 Figure 74. Addressing the Flash during SPM BIT 15 ZPCMSB Z - REGISTER PCMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE Notes: 1. The different variables used in Figure 74 are ...
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Performing Page Erase by SPM Filling the Temporary Buffer (page loading) Performing a Page Write Using the SPM Interrupt Consideration While Updating BLS Prevent Reading the RWW Section During Self- Programming 2512K–AVR–01/10 To execute Page Erase, set up the address ...
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Setting the Boot Loader Lock bits by SPM EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock bits from Software ATmega8515(L) 174 To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to ...
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Preventing Flash Corruption Programming Time for Flash when using SPM Simple Assembly Code Example for a Boot Loader 2512K–AVR–01/10 During periods of low V the Flash program can be corrupted because the supply volt- CC, age is too low for ...
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ATmega8515(L) 176 ; re-enable the RWW section ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN) rcallDo_spm ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ldi loophi, high(PAGESIZEB) Wrloop r1, Y+ ldi spmcrval, (1<<SPMEN) rcallDo_spm adiw ...
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ATmega8515 Boot Loader Parameters 2512K–AVR–01/10 ; input: spmcrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed ...
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ATmega8515(L) 178 Table 80. Explanation of Different Variables used in Figure 74 and the Mapping to the (1) Z-pointer Corresponding Variable Z-value PCMSB 11 PAGEMSB 4 ZPCMSB Z12 ZPAGEMSB Z5 PCPAGE PC[11:5] Z12:Z6 PCWORD PC[4:0] Z5:Z1 Note: 1. Z15:Z13: always ...
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Memory Programming Program and Data Memory Lock bits 2512K–AVR–01/10 The ATmega8515 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 82. The Lock bits can only ...
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Fuse bits ATmega8515(L) 180 Table 82. Lock Bit Protection Modes Memory Lock bits Protection Type No restrictions for SPM or LPM accessing the Boot Loader section SPM is not allowed to write to the ...
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... EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. All Atmel microcontrollers have a 3-byte signature code which identifies the device. This code can be read in both Serial and Parallel mode, also when the device is locked. The three bytes reside in a separate address space ...
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Parallel Programming Parameters, Pin Mapping, and Commands Signal Names ATmega8515(L) 182 This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8515. Pulses are assumed to be ...
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Table 86. Pin Values used to Enter Programming Mode Pin PAGEL XA1 XA0 BS1 Table 87. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte ...
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Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase ATmega8515(L) 184 The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5 V between Set RESET to “0”, wait for at ...
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Programming the Flash 2512K–AVR–01/10 The Flash is organized in pages, see Table 89 on page 183. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. ...
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ATmega8515(L) 186 3. Wait until RDY/BSY goes high. (See Figure 77 for signal waveforms) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, ...
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Programming the EEPROM 2512K–AVR–01/10 Figure 77. Programming the Flash Waveforms $10 ADDR. LOW DATA LOW DATA HIGH DATA XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: “XX” is don’t care. The letters ...
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Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits ATmega8515(L) 188 Figure 78. Programming the EEPROM Waveforms $11 ADDR. HIGH ADDR. LOW DATA XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET ...
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Programming the Lock bits Reading the Fuse and Lock bits 2512K–AVR–01/ Load Command “0100 0000” Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 ...
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Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics ATmega8515(L) 190 Figure 80. Mapping Between BS1, BS2, and the Fuse- and Lock bits During Read Fuse Low Byte Lock Bits Fuse High Byte BS2 The algorithm for reading ...
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Figure 82. Parallel Programming Timing, Loading Sequence with Timing (1) Requirements LOAD ADDRESS LOAD DATA (LOW BYTE) (LOW BYTE) XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 81 (i.e. t ...
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ATmega8515(L) 192 Table 91. Parallel Programming Characteristics, V Symbol Parameter t XTAL1 Low to WR Low XLWL t XTAL1 Low to PAGEL high XLPH t PAGEL low to XTAL1 high PLXH t BS1 Valid before PAGEL High BVPH t PAGEL ...
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Serial Downloading Serial Programming Pin Mapping 2512K–AVR–01/10 Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). ...
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Serial Programming Algorithm Data Polling Flash ATmega8515(L) 194 When writing serial data to the ATmega8515, data is clocked on the rising edge of SCK. When reading data from the ATmega8515, data is clocked on the falling edge of SCK. See ...
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Data Polling EEPROM 2512K–AVR–01/10 When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the ...
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Table 94. Serial Programming Instruction Set Instruction Byte 1 1010 1100 Programming Enable Chip Erase 1010 1100 0010 H000 Read Program memory 0100 H000 Load Program memory Page Write Program memory 0100 1100 Page 1010 0000 Read EEPROM Memory 1100 ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating ...
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DC Characteristics (Continued -40°C to 85° 2.7V to 5.5V (Unless Otherwise Noted Symbol Parameter Power Supply Current I CC (5) Power-down mode Analog Comparator V ACIO Input Offset Voltage Analog Comparator I ACLK Input ...
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External Clock Drive Waveforms External Clock Drive 2512K–AVR–01/10 Figure 86. External Clock Drive Waveforms V IH1 V IL1 Table 95. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time ...
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SPI Timing Characteristics ATmega8515(L) 200 See Figure 87 and Figure 88 for details. Table 97. SPI Timing Parameters Description Mode 1 SCK period Master 2 SCK high/low Master 3 Rise/Fall time Master 4 Setup Master 5 Hold Master 6 Out ...