ATTINY26-16PC Atmel, ATTINY26-16PC Datasheet - Page 23
![IC AVR MCU 2K 16MHZ COM 20-DIP](/photos/6/80/68043/313-20-dip_sml.jpg)
ATTINY26-16PC
Manufacturer Part Number
ATTINY26-16PC
Description
IC AVR MCU 2K 16MHZ COM 20-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY26-16PC
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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System Clock
and Clock
Options
Clock Systems
and their
Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
ADC Clock – clk
1477K–AVR–08/10
I/O
CPU
ADC
FLASH
Figure 20 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 37. The clock systems are detailed below.
Figure 20. Clock Distribution
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, and USI. The I/O
clock is also used by the External Interrupt module, but note that some external interrupts are
detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is
halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
clk
Timer/Counter1
PCK
PLL
clk
PLL
External RC
General I/O
Oscillator
modules
clk
I/O
Multiplexer
External clock
Control Unit
AVR Clock
Clock
ADC
Source clock
clk
ADC
clk
Oscillator
clk
Crystal
CPU
FLASH
Reset Logic
CPU Core
Crystal Oscillator
Low-Frequency
Watchdog clock
RAM
Watchdog Timer
Watchdog
Oscillator
Calibrated RC
Flash and
EEPROM
Oscillator
23
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