AT89S51-24JI Atmel, AT89S51-24JI Datasheet - Page 15
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AT89S51-24JI
Manufacturer Part Number
AT89S51-24JI
Description
IC 8051 MCU 4K FLASH 44PLCC
Manufacturer
Atmel
Series
89Sr
Datasheet
1.AT89S51-24JU.pdf
(31 pages)
Specifications of AT89S51-24JI
Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89S51-24JI
Manufacturer:
ATMEL
Quantity:
13 888
Part Number:
AT89S51-24JI
Manufacturer:
AT
Quantity:
20 000
16. Programming the Flash – Serial Mode
16.1
2487D–MICRO–6/08
Serial Programming Algorithm
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code
data can be read back via the address and data lines for verification. The status of the individ-
ual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-
mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to
a logic low. The values returned are as follows.
Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the
proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -
500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase
instruction. In this mode, chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location will return 00H at the data output.
The Code memory array can be programmed using the serial ISP interface while RST is pulled
to V
set high, the Programming Enable instruction needs to be executed first before other operations
can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is
required.
The Chip Erase operation turns the content of every memory location in the Code array into
FFH.
Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than
1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is
2 MHz.
To program and verify the AT89S51 in the serial programming mode, the following sequence is
recommended:
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to
XTAL1 pin and wait for at least 10 milliseconds.
1. Power-up sequence:
2. Enable serial programming by sending the Programming Enable serial instruction to pin
3. The Code array is programmed one byte at a time in either the Byte or Page mode. The
4. Any memory location can be verified by using the Read instruction that returns the con-
CC
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H indicates AT89S51
(200H) = 06H
a. Apply power between VCC and GND pins.
b. Set RST pin to “H”.
MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less
than the CPU clock at XTAL1 divided by 16.
write cycle is self-timed and typically takes less than 0.5 ms at 5V.
tent at the selected address at serial output MISO/P1.6.
. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is
AT89S51
15