ATMEGA162V-1PC Atmel, ATMEGA162V-1PC Datasheet - Page 205

• Manufacturer Part Number: ATMEGA162V-1PC
• Description: IC MCU AVR 16K 1.8V 8MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-1PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Boundary-scan Chain
Scanning the Digital Port Pins Figure 87 shows the Boundary-scan Cell for a bi-directional port pin with pull-up func-
2513C–AVR–09/02
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
The Boundary-scan Chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having Off-chip connection.
tion. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn
– function, and a bi-directional pin cell that combines the three signals Output Control –
OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.
The port and pin indexes are not used in the following description
The Boundary-scan logic is not included in the figures in the Data Sheet. Figure 88
shows a simple digital Port Pin as described in the section “I/O-Ports” on page 61. The
Boundary-scan details from Figure 87 replaces the dashed box in Figure 88.
When no alternate port function is present, the Input Data – ID – corresponds to the
PINxn Register value (but ID has no synchronizer), Output Data corresponds to the
PORT Register, Output Control corresponds to the Data Direction – DD Register, and
the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 88 to
make the scan chain read the actual pin value. For Analog function, there is a direct
connection from the external pin to the analog circuit, and a scan chain is inserted on
the interface between the digital logic and the analog circuitry.
ATmega162(V/U/L)
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