PIC16LF87T-I/ML Microchip Technology, PIC16LF87T-I/ML Datasheet - Page 4

• Manufacturer Part Number: PIC16LF87T-I/ML
• Description: IC MCU FLASH 4KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF87T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC16F87/88
Change 6. Section 4.7.1
If the system clock does not come from the INTRC
(31.25 kHz) when the SCS bits are changed, and the
IRCF bits in the OSCCON register are configured for a
frequency other than INTRC, the frequency may not be
stable immediately. The IOFS bit (OSCCON<2>) will
be set when the INTOSC or postscaler frequency is
stable, after approximately 100 μs.
TABLE 4-4:
DS80365A-page 4
Note 1:
LP, XT, HS,
LP, XT, HS,
LP, XT, HS
Current
T1OSC,
System
EC, RC
INTRC,
EC, RC
T1OSC
T1OSC
INTRC
INTRC
Clock
The second paragraph in Section 4.7.1 “RC_RUN
Mode” is changed as shown.
If the new clock source is the INTOSC or INTOSC postscaler, the IOFS bit will be set approximately
100 μs after the clock change.
FOSC<2:0> = LP,
FOSC<2:0> = LP,
FOSC<2:0> = EC
FOSC<2:0> = RC
FOSC<2:0> = LP,
SCS Bits <1:0>
(Due to Reset)
Modified to:
LP, XT, HS
CLOCK SWITCHING MODES
XT or HS
XT or HS
(T1OSC)
(INTRC)
XT, HS
10
01
00
00
00
or
1024 Clocks
1024 Clocks
8 Clocks of
8 Clocks of
8 Clocks of
8 Clocks of
LP, XT, HS
T1OSC
INTRC
(OST)
(OST)
Delay
EC
RC
or
+
OSTS
Bit
0
0
1
1
1
IOFS
1
N/A
N/A
N/A
N/A
Bit
(1)
Change 7. Table 4-4
T1RUN
Bit
0
1
0
0
0
The note in Table 4-4 is changed as shown.
LP, XT, HS During the 1024 clocks,
LP, XT, HS When a Reset occurs, there is
Postscaler
INTOSC
INTOSC
System
T1OSC
INTRC
Clock
New
EC
RC
or
or
or
The internal RC oscillator
frequency is dependant upon
the IRCF bits.
T1OSCEN bit must be
enabled.
program execution is clocked
from the secondary oscillator
until the primary oscillator
becomes stable.
no clock transition sequence.
Instruction execution and/or
peripheral operation is
suspended unless Two-Speed
Start-up mode is enabled, after
which the INTRC will act as the
system clock until the OST
timer has expired.
© 2008 Microchip Technology Inc.
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