PIC16F874A-E/ML Microchip Technology, PIC16F874A-E/ML Datasheet - Page 325
PIC16F874A-E/ML
Manufacturer Part Number
PIC16F874A-E/ML
Description
IC MCU FLASH 4KX14 A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F874A-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- PIC16F873A-ISO PDF datasheet #9
- Current page: 325 of 688
- Download datasheet (3Mb)
17.4.18
1997 Microchip Technology Inc.
SDA
SCL
BCLIF
Multi -Master Communication, Bus Collision, and Bus Arbitration
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data
bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA by letting
SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be
stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus
collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset
the I
If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF
flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When
the user services the bus collision interrupt service routine, and if the I
can resume communication by asserting a START condition.
If a START, Repeated Start, STOP, or Acknowledge condition was in progress when the bus col-
lision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respec-
tive control bits in the SSPCON2 register are cleared. When the user services the bus collision
interrupt service routine, and if the I
ing a START condition.
The Master will continue to monitor the SDA and SCL pins, and if a STOP condition occurs, the
SSPIF bit will be set.
A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where
the transmitter left off when bus collision occurred.
In multi-master mode, the interrupt generation on the detection of start and stop conditions allows
the determination of when the bus is free. Control of the I
set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared.
Figure 17-34: Bus Collision Timing for Transmit and Acknowledge
2
C port to its IDLE state.
Data changes
while SCL = 0
SDA released
by master
Preliminary
(Figure
SDA line pulled low
by another source
2
C bus is free, the user can resume communication by assert-
17-34).
Section 17. MSSP
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
2
C bus can be taken when the P bit is
Set bus collision
interrupt (BCLIF).
2
C bus is free, the user
DS31017A-page 17-49
17
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