PIC16F77T-E/ML Microchip Technology, PIC16F77T-E/ML Datasheet - Page 303
![IC MCU FLASH 8KX14 A/D 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC16F77T-E/ML
Manufacturer Part Number
PIC16F77T-E/ML
Description
IC MCU FLASH 8KX14 A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F77T-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
3 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 303 of 688
- Download datasheet (3Mb)
17.4.3
17.4.4
INTCON
PIR
PIE
SSPADD
SSPBUF
SSPCON1 WCOL
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Note 1: The position of these bits is device dependent.
1997 Microchip Technology Inc.
Name
2: These bits may also be named GPIE and GPIF.
Shaded cells are not used by the SSP in I
Sleep Operation
Effect of a Reset
Synchronous Serial Port (I
Address Register (slave mode)/Baud Rate Generator (master mode)
Synchronous Serial Port Receive Buffer/Transmit Register
Bit 7
SMP
GIE
While in sleep mode, the I
or complete byte transfer occurs wake the processor from sleep (if the MSSP interrupt is
enabled).
A reset disables the MSSP module and terminates the current transfer.
Table 17-3: Registers Associated with I
SSPOV
PEIE
Bit 6
CKE
SSPEN
Bit 5
T0IE
D/A
2
SSPIE, BCLIF
C mode)
SSPIF, BCLIF
INTE
Bit 4
CKP
P
2
C module can receive addresses or data, and when an address match
Preliminary
2
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
RBIE
C mode.
Bit 3
S
(1)
(2)
(1)
Bit 2
T0IF
PEN
R/W
2
C Operation
Section 17. MSSP
RSEN
INTF
Bit 1
UA
RBIF
Bit 0
SEN
BF
(2)
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
Value on
POR,
BOR
0, 0
0, 0
DS31017A-page 17-27
other resets
Value on all
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0, 0
0, 0
17
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