PIC16LF819T-E/SS Microchip Technology, PIC16LF819T-E/SS Datasheet - Page 42
![IC PIC MCU FLASH 2KX14 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16LF819T-E/SS
Manufacturer Part Number
PIC16LF819T-E/SS
Description
IC PIC MCU FLASH 2KX14 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF819T-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F2450/4450
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• The primary clock source is not any of the XT or
TABLE 3-2:
DS39760D-page 40
Note 1:
is not stopped; and
HS modes
Primary Device Clock
T1OSC or INTRC
2:
3:
4:
(PRI_IDLE mode)
Before Wake-up
(Sleep mode)
In this instance, refers specifically to the 31 kHz INTRC clock source.
T
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
T
(parameter F12, Table 21-7); it is also designated as T
Execution continues during T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
INTRC
CSD
OST
None
(parameter 38, Table 21-10) is a required delay when waking from Sleep and all Idle modes and runs
is the Oscillator Start-up Timer period (parameter 32, Table 21-10). t
Microcontroller Clock Source
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(1)
(1)
IOBST
XTPLL, HSPLL
XTPLL, HSPLL
XTPLL, HSPLL
XTPLL, HSPLL
After Wake-up
INTRC
INTRC
INTRC
INTRC
XT, HS
XT, HS
XT, HS
XT, HS
(parameter 39, Table 21-10), the INTRC stabilization period.
EC
EC
EC
EC
(1)
(1)
(1)
(1)
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
PLL
.
following the wake event is still required when
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
IOBST
IOBST
None
None
CSD
CSD
CSD
OST
OST
OST
+ t
+ t
+ t
(3)
(2)
(3)
(2)
(3)
(2)
rc
(4)
rc
rc
(4)
(3)
(3)
(3)
rc
is the PLL lock time-out
© 2008 Microchip Technology Inc.
Clock Ready Status
Bit (OSCCON)
OSTS
OSTS
OSTS
OSTS
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