PIC16LF74-I/PTG Microchip Technology, PIC16LF74-I/PTG Datasheet - Page 81
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PIC16LF74-I/PTG
Manufacturer Part Number
PIC16LF74-I/PTG
Description
IC MCU FLASH 4KX14 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF74-I/PTG
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF74-I/PTG
Manufacturer:
Microchip Technology
Quantity:
10 000
10.3.2
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>),
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is con-
tinuous until CREN is cleared. If both bits are set, CREN
takes precedence. After clocking the last bit, the
received data in the Receive Shift Register (RSR) is
transferred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is reset by the
hardware. In this case, it is reset when the RCREG reg-
ister has been read and is empty. The RCREG is a dou-
ble buffered register (i.e., it is a two deep FIFO). It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin shift-
ing into the RSR register. On the clocking of the last bit
of the third byte, if the RCREG register is still full, then
overrun error bit OERR (RCSTA<1>) is set. The word in
the RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Bit OERR has
to be cleared in software (by clearing bit CREN). If bit
OERR is set, transfers from the RSR to the RCREG are
inhibited, so it is essential to clear bit OERR if it is set.
The ninth receive bit is buffered the same way as the
FIGURE 10-8:
2002 Microchip Technology Inc.
Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRG = ’0’.
RC7/RX/DT pin
RC6/TX/CK pin
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
Read
USART SYNCHRONOUS MASTER
RECEPTION
Q2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
’0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit0
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit1
bit2
bit3
receive data. Reading the RCREG register will load bit
RX9D with a new value, therefore, it is essential for the
user to read the RCSTA register before reading RCREG,
in order not to lose the old RX9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that GIE and PEIE in
Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
the INTCON register are set.
bit4
bit5
bit6
PIC16F7X
bit7
DS30325B-page 79
Q1 Q2 Q3 Q4
’0’