AT89C5122D-RDVIM Atmel, AT89C5122D-RDVIM Datasheet - Page 117
AT89C5122D-RDVIM
Manufacturer Part Number
AT89C5122D-RDVIM
Description
IC 8051 MCU W/SMART CARD 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C5122D-PSTUM.pdf
(208 pages)
Specifications of AT89C5122D-RDVIM
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT89C5122D-RDTIM
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4202F–SCR–07/2008
Table 66. USB Global Interrupt Enable Register - USBIEN (S:BEh)
Reset Value = 0001 0000b
Table 67. USB Address Register - USBADDR (S:C6h)
Reset Value = 1000 0000b
Bit Number
Number
Bit
6-0
FEN
7 - 6
2-1
7
7
7
-
5
4
3
0
Mnemonic Description
UADD[6:0]
Mnemonic Description
EWUPCPU
EEORINT
ESOFINT
UADD6
ESPINT
FEN
Bit
Bit
6
6
-
-
-
Function Enable
Set this bit to enable the function. FADD is reset to 1.
Cleared this bit to disable the function.
USB Address
This field contains the default address (0) after power-up or USB bus reset.
It should be written with the value set by a SET_ADDRESS request received by
the device firmware.
Reserved
The value read from these bits is always 0. Do not change these bits.
Enable Wake-up CPU Interrupt
Set this bit to enable Wake-up CPU Interrupt.
Clear this bit to disable Wake-up CPU Interrupt.
Enable End of Reset Interrupt
Set this bit to enable End of Reset Interrupt. This bit is set after reset.
Clear this bit to disable End of Reset Interrupt.
Enable SOF Interrupt
Set this bit to enable SOF Interrupt.
Clear this bit to disable SOF Interrupt.
Reserved
The value read from these bits is always 0. Do not change these bits.
Enable Suspend Interrupt
Set this bit to enable Suspend Interrupts (See Table 65 on page 116).
Clear this bit to disable Suspend Interrupts.
EWUPCPU
UADD5
5
5
EEORINT
UADD4
AT83R5122, AT8xC5122/23
4
4
ESOFINT
UADD3
3
3
UADD2
2
2
-
UADD1
1
1
-
ESPINT
UADD0
0
0
117
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