AT89C5131A-RDTIL Atmel, AT89C5131A-RDTIL Datasheet - Page 92

• Manufacturer Part Number: AT89C5131A-RDTIL
• Description: IC 8051 MCU FLASH 32K USB 64VQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-RDTIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: AT89C5131-RDTIL

Functional Description
Operating Modes
92
AT89C5131A-L
Figure 43 shows a detailed structure of the SPI module.
Figure 43. SPI Module Block Diagram
The Serial Peripheral Interface can be configured as one of the two modes: Master
mode or Slave mode. The configuration and initialization of the SPI module is made
through one register:
•
Once the SPI is configured, the data exchange is made using:
•
•
•
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 44).
SPI Interrupt Request
The Serial Peripheral CONtrol register (SPCON)
SPCON
The Serial Peripheral STAtus register (SPSTA)
The Serial Peripheral DATa register (SPDAT)
Clock
Divider
FCLK PERIPH
SPR2
/128
/32
/64
/16
SPEN
/4
/8
Clock
Select
SSDIS
MSTR
SPIF
Receive Data Register
CPOL
WCOL
7
Shift Register
Internal Bus
6
SPI
Control
CPHA
5
SSERR
4
3
SPR1
2
Clock
Logic
SPCON
1
SPDAT
MODF
0
SPR0
-
M
Pin
Control
Logic
S
-
-
SPSTA
4338F–USB–08/07
-
8-bit bus
1-bit signal
MOSI
MISO
SCK
SS