ATMEGA162-16AJ Atmel, ATMEGA162-16AJ Datasheet - Page 112
![IC MCU AVR 16K 5V 16MHZ 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA162-16AJ
Manufacturer Part Number
ATMEGA162-16AJ
Description
IC MCU AVR 16K 5V 16MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA162-16AJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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Timer/Counter
Clock Sources
Counter Unit
112
ATmega162/V
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located
in the Timer/Counter Control Register B (TCCRnB). For details on clock sources and prescaler,
see
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 47
Figure 47. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-
taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight
bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNTnH value when the TCNTnL is read, and
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each Timer Clock (clk
source, selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 =
0) the Timer is stopped. However, the TCNTn value can be accessed by the CPU, independent
of whether clk
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OCnx. For more details about advanced counting
sequences and waveform generation, see
Count
Direction
Clear
clk
TOP
BOTTOM
“Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers” on page
T
n
shows a block diagram of the counter and its surroundings.
TCNTnH (8-bit)
TEMP (8-bit)
Increment or decrement TCNTn by 1.
Select between increment and decrement.
Clear TCNTn (set all bits to zero).
Timer/Counter clock.
Signalize that TCNTn has reached maximum value.
Signalize that TCNTn has reached minimum value (zero).
T
n
TCNTn (16-bit Counter)
DATA BUS
is present or not. A CPU write overrides (has priority over) all counter clear or
TCNTnL (8-bit)
T
n
(8-bit)
). The clk
T
n
Direction
can be generated from an external or internal clock
Count
Clear
“Modes of Operation” on page
Control Logic
TOP
BOTTOM
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
118.
104.
2513K–AVR–07/09
Tn
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