ATMEGA48-20MJ Atmel, ATMEGA48-20MJ Datasheet - Page 209
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ATMEGA48-20MJ
Manufacturer Part Number
ATMEGA48-20MJ
Description
IC AVR MCU 4K 5V 20MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48-20MJ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA48-24MJ
ATMEGA48-24MJ
ATMEGA48-24MJ
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21.2.2
21.3
21.3.1
21.3.2
2545S–AVR–07/10
Data Transfer and Frame Format
Electrical Interconnection
Transferring Bits
START and STOP Conditions
Table 21-1.
The PRTWI bit in
the 2-wire Serial Interface.
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line
high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,
and one valid for bus speeds up to 400 kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 21-2. Data Validity
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
Term
Slave
Transmitter
Receiver
SDA
SCL
TWI Terminology
Figure
Description
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
“Minimizing Power Consumption” on page 40
21-1, both bus lines are connected to the positive supply voltage through
Data Stable
“2-wire Serial Interface Characteristics” on page
Data Change
Data Stable
ATmega48/88/168
must be written to zero to enable
307. Two
209
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