ATMEGA8535-16PJ Atmel, ATMEGA8535-16PJ Datasheet - Page 119
![IC MCU AVR 8K 5V 16MHZ 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8535-16PJ
Manufacturer Part Number
ATMEGA8535-16PJ
Description
IC MCU AVR 8K 5V 16MHZ 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16PJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Counter Unit
Output Compare Unit
2502K–AVR–10/06
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 54 shows a block diagram of the counter and its surrounding environment.
Figure 54. Counter Unit Block Diagram
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or dec-
remented at each timer clock (clk
clock source, selected by the Clock Select bits (CS22:0). When no clock source is
selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed
by the CPU, regardless of whether clk
priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits
located in the Timer/Counter Control Register (TCCR2). There are close connections
between how the counter behaves (counts) and how waveforms are generated on the
output compare output OC2. For more details about advanced counting sequences and
waveform generation, see “Modes of Operation” on page 122.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation
selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will
set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 =
1), the Output Compare Flag generates an output compare interrupt. The OCF2 Flag is
automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can
be cleared by software by writing a logical one to its I/O bit location. The Waveform Gen-
erator uses the match signal to generate an output according to operating mode set by
the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom sig-
nals are used by the Waveform Generator for handling the special cases of the extreme
values in some modes of operation (see “Modes of Operation” on page 122).
Figure 55 shows a block diagram of the output compare unit.
count
direction
clear
clk
top
bottom
T2
DATA BUS
TCNTn
Increment or decrement TCNT2 by 1.
Selects between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/Counter clock.
Signalizes that TCNT2 has reached maximum value.
Signalizes that TCNT2 has reached minimum value (zero).
direction
count
clear
bottom
Control Logic
T2
). clk
top
T2
TOVn
(Int.Req.)
T2
is present or not. A CPU write overrides (has
clk
can be generated from an external or internal
Tn
Prescaler
ATmega8535(L)
Oscillator
T/C
clk
I/O
TOSC2
TOSC1
119
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