ATTINY13-20SSI Atmel, ATTINY13-20SSI Datasheet - Page 34

• Manufacturer Part Number: ATTINY13-20SSI
• Description: IC MCU AVR 1K FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY13-20SSI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Connectivity: -
• Lead Free Status / Rohs Status: No
• Other names: ATTINY13-24SSI; ATTINY13-24SSI

8. System Control and Reset
8.0.1
34
ATtiny13
Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in
Reset Characteristics” on page 119
Figure 8-1.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL fuses. The differ-
ent selections for the delay period are presented in
BODLEVEL [1..0]
Reset Logic
Pull-up Resistor
FILTER
SPIKE
CKSEL[1:0]
Power-on Reset
Reset Circuit
Figure 8-1 on page 34
SUT[1:0]
Brown-out
Watchdog
Oscillator
Generator
defines the electrical parameters of the reset circuitry.
Circuit
Clock
CK
Register (MCUSR)
“Clock Sources” on page
MCU Status
DATA BUS
Delay Counters
shows the reset logic.
TIMEOUT
24.
2535J–AVR–08/10
“System and