AT80C51RD2-3CSIM Atmel, AT80C51RD2-3CSIM Datasheet - Page 59

• Manufacturer Part Number: AT80C51RD2-3CSIM
• Description: IC MCU 8051 5V SPI 20MHZ 40-DIP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51RD2-3CSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

15.2
4113D–8051–01/09
WDT During Power-down and Idle
Table 15-2.
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode the user does not need to service the WDT. There are 2 methods of exiting Power-
down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power-down mode. When Power-down is exited with hardware reset, servicing the
WDT should occur as normal, whenever the AT80C51RD2 is reset. Exiting Power-down with an
interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabi-
lize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down, it is bet-
ter to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT80C51RD2 while in Idle mode, the user should always set up a timer that will periodically exit
Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
7
6
5
4
3
2
1
0
-
WDTPRG Register
Mnemonic Description
Bit
S2
S1
S0
6
-
-
-
-
-
-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2S1 S0Selected Time-out
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
5
-
0
1
0 (2
1
0
1 (2
0
1
16
19
- 1) machine cycles, 65. 5 ms @ F
- 1) machine cycles, 542 ms @ F
(2
(2
(2
(2
(2
(2
14
15
17
18
20
21
4
-
- 1) machine cycles, 16. 3 ms @ F
- 1) machine cycles, 32.7 ms @ F
- 1) machine cycles, 131 ms @ F
- 1) machine cycles, 262 ms @ F
- 1) machine cycles, 1.05 s @ F
- 1) machine cycles, 2.09 s @ F
3
-
S2
2
osc
osc
AT80C51RD2
=12 MHz
=12 MHz
osc
osc
osc
osc
osc
=12 MHz
=12 MHz
osc
=12 MHz
=12 MHz
=12 MHz
=12 MHz
S1
1
S0
0
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