DSPIC30F6014A-20I/PT Microchip Technology, DSPIC30F6014A-20I/PT Datasheet - Page 20

• Manufacturer Part Number: DSPIC30F6014A-20I/PT
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6014A-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: DSPIC30F6014A20IP

dsPIC30F6011A/6012A/6013A/6014A
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The fol-
lowing instructions and data sizes are supported:
1.
2.
3.
4.
5.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
DS70143B-page 18
DIVF
DIV.sd
DIV.sw or DIV.s Signed divide: Wm/Wn
DIV.ud
DIV.uw or DIV.u Unsigned divide: Wm/Wn
DIVF - 16/16 signed fractional divide
DIV.sd - 32/16 signed divide
DIV.ud - 32/16 unsigned divide
DIV.sw - 16/16 signed divide
DIV.uw - 16/16 unsigned divide
Instruction
Divide Support
DIVIDE INSTRUCTIONS
Signed fractional divide: Wm/Wn
Signed divide: (Wm + 1:Wm)/Wn
Unsigned divide: (Wm + 1:Wm)/Wn
W0; Rem
W0; Rem
Preliminary
W0; Rem
W0; Rem
W0; Rem
W1
W1
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion as shown in Table 2-1 (REPEAT will execute the tar-
get instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
Function
Note:
W1
W1
W1
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
© 2005 Microchip Technology Inc.