ATTINY25-20SI Atmel, ATTINY25-20SI Datasheet - Page 132
![IC AVR MCU 2K 20MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY25-20SI
Manufacturer Part Number
ATTINY25-20SI
Description
IC AVR MCU 2K 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY25-20SI
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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17.6
17.6.1
17.6.2
17.7
132
Changing Channel or Reference Selection
ADC Noise Canceler
ATtiny25/45/85
ADC Input Channels
ADC Voltage Reference
The MUX[3:0] and REFS[2:0] bits in the ADMUX Register are single buffered through a tempo-
rary register to which the CPU has random access. This ensures that the channels and voltage
reference selection only takes place at a safe point during the conversion. The channel and volt-
age reference selection is continuously updated until a conversion is started. Once the
conversion starts, the channel and voltage reference selection is locked to ensure a sufficient
sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the
conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following
rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel
or voltage reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the channel
selection. Since the next conversion has already started automatically, the next result will reflect
the previous channel selection. Subsequent conversions will reflect the new channel selection.
The voltage reference for the ADC (V
ended channels that exceed V
either V
version result after switching voltage reference source may be inaccurate, and the user is
advised to discard this result.
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise
induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
CC
, or internal 1.1V / 2.56V voltage reference, or external AREF pin. The first ADC con-
REF
will result in codes close to 0x3FF. V
REF
) indicates the conversion range for the ADC. Single
REF
can be selected as
2586M–AVR–07/10
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