ATMEGA8535-16AU Atmel, ATMEGA8535-16AU Datasheet - Page 126
ATMEGA8535-16AU
Manufacturer Part Number
ATMEGA8535-16AU
Description
IC AVR MCU 8K 16MHZ 5V 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
ATMEGA8x
Core
AVR8
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8535-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Timer/Counter Timing
Diagrams
126
ATmega8535(L)
between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
The “N” variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
At the very start of period 2 in Figure 59 OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
•
•
The following figures show the Timer/Counter in Synchronous mode, and the Timer
Clock (clk
should be replaced by the Timer/Counter Oscillator clock. The figures include informa-
tion on when interrupt flags are set. Figure 60 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value
in all modes other than phase correct PWM mode.
Figure 60. Timer/Counter Timing Diagram, no Prescaling
Figure 61 shows the same timing data, but with the prescaler enabled.
TCNTn
(clk
TOVn
clk
clk
I/O
OCR2 changes its value from MAX, like in Figure 59. When the OCR2 value is MAX
the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the
result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR2, and for that
reason misses the Compare Match and hence the OCn change that would have
happened on the way up.
I/O
Tn
/1)
T2
) is therefore shown as a clock enable signal. In Asynchronous mode, clk
MAX - 1
f
OCnPCPWM
MAX
=
----------------- -
N 510
f
clk_I/O
⋅
BOTTOM
2502K–AVR–10/06
BOTTOM + 1
I/O
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