DSPIC30F3010T-20I/ML Microchip Technology, DSPIC30F3010T-20I/ML Datasheet - Page 136

• Manufacturer Part Number: DSPIC30F3010T-20I/ML
• Description: IC DSPIC MCU/DSP 24K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• For Use With: XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F3010/3011
20.2.7
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM configuration bits (Clock
Switch and Monitor Selection bits) in the F
Configuration register. If the FSCM function is
enabled, the LPRC Internal oscillator will run at all
times (except during Sleep mode) and will not be
subject to control by the SWDTEN bit.
In the event of an oscillator failure, the FSCM will
generate a Clock Failure Trap event and will switch the
system clock over to the FRC oscillator. The user will
then have the option to either attempt to restart the
oscillator or execute a controlled shutdown. The user
may decide to treat the Trap as a warm Reset by simply
loading the Reset address into the oscillator fail trap
vector. In this event, the CF (Clock Fail) status bit
(OSCCON<3>) is also set whenever a clock failure is
recognized.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If the oscillator has a very slow start-up time coming
out of POR, BOR or Sleep, it is possible that the
PWRT timer will expire before the oscillator has
started. In such cases, the FSCM will be activated and
the FSCM will initiate a clock failure trap, and the
COSC<1:0> bits are loaded with FRC oscillator selec-
tion. This will effectively shut-off the original oscillator
that was trying to start.
The user may detect this situation and restart the
oscillator in the clock fail trap ISR.
Upon a clock failure detection, the FSCM module will
initiate a clock switch to the FRC Oscillator as follows:
1.
2.
3.
For the purpose of clock switching, the clock sources
are sectioned into four groups:
1.
2.
3.
4.
The user can switch between these functional groups,
but cannot switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR<4:0>
configuration bits.
DS70141B-page 134
The COSC bits (OSCCON<13:12>) are loaded
with the FRC Oscillator selection value.
CF bit is set (OSCCON<3>).
OSWEN control bit (OSCCON<0>) is cleared.
Primary
Secondary
Internal FRC
Internal LPRC
FAIL-SAFE CLOCK MONITOR
OSC
Device
Preliminary
The OSCCON register holds the control and status bits
related to clock switching.
• COSC<1:0>: Read only status bits always reflect
• NOSC<2:0>: Control bits which are written to
• LOCK: The LOCK status bit indicates a PLL lock.
• CF: Read only status bit indicating if a clock fail
• OSWEN: Control bit changes from a ‘0’ to a ‘1’
If configuration bits FCKSM<1:0> = 1x, then the clock
switching and fail-safe clock monitor functions are
disabled. This is the default configuration bit setting.
If clock switching is disabled, then the FOS<1:0> and
FPR<3:0> bits directly control the oscillator selection
and the COSC<1:0> bits do not control the clock
selection. However, these bits will reflect the clock
source selection.
20.2.8
A write to the OSCCON register is intentionally made
difficult because it controls clock switching and clock
scaling.
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
Byte Write is allowed for one instruction cycle . Write the
desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
:
Byte Write is allowed for one instruction cycle . Write the
desired value or use bit manipulation instruction.
Byte Write “0x46” to OSCCON low
Byte Write “0x57” to OSCCON low
Byte Write “0x78” to OSCCON high
Byte Write “0x9A” to OSCCON high
the current oscillator group in effect.
indicate the new oscillator group of choice.
- On POR and BOR, COSC<1:0> and
detect has occurred.
when a clock transition sequence is initiated.
Clearing the OSWEN control bit will abort a clock
transition in progress (used for hang-up
situations).
Note:
NOSC<1:0> are both loaded with the
configuration bit values FOS<1:0>.
The application should not attempt to
switch to a clock of frequency lower than
100 kHz when the fail-safe clock monitor is
enabled. If such clock switching is
performed, the device may generate an
oscillator fail trap and switch to the fast RC
oscillator.
PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
© 2005 Microchip Technology Inc.