DSPIC30F6012AT-20I/PT Microchip Technology, DSPIC30F6012AT-20I/PT Datasheet - Page 234

• Manufacturer Part Number: DSPIC30F6012AT-20I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012AT-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F6011A/6012A/6013A/6014A
Trap Vectors........................................................................ 48
Traps ................................................................................... 47
U
UART Module
UART Operation
Unit ID Locations............................................................... 143
Universal Asynchronous Receiver Transmitter. See UART
W
Wake-up from Sleep ......................................................... 143
Wake-up from Sleep and Idle.............................................. 49
Watchdog Timer (WDT) ............................................ 143, 158
WWW Address.................................................................. 233
WWW, On-Line Support........................................................ 8
DS70143B-page 232
Hard and Soft .............................................................. 48
Sources ....................................................................... 47
Address Detect Mode ............................................... 107
Auto Baud Support.................................................... 108
Baud Rate Generator ................................................ 107
Enabling and Setting Up ........................................... 105
Framing Error (FERR)............................................... 107
Idle Status ................................................................. 107
Loopback Mode ........................................................ 107
Operation During CPU Sleep and Idle Modes .......... 108
Overview ................................................................... 103
Parity Error (PERR) .................................................. 107
Receive Break........................................................... 107
Receive Buffer (UxRXB) ........................................... 106
Receive Buffer Overrun Error (OERR Bit) ................ 106
Receive Interrupt....................................................... 106
Receiving Data.......................................................... 106
Receiving in 8-bit or 9-bit Data Mode........................ 106
Reception Error Handling.......................................... 106
Transmit Break.......................................................... 106
Transmit Buffer (UxTXB)........................................... 105
Transmit Interrupt...................................................... 106
Transmitting Data...................................................... 105
Transmitting in 8-bit Data Mode ................................ 105
Transmitting in 9-bit Data Mode ................................ 105
UART1 Register Map ................................................ 109
UART2 Register Map ................................................ 109
Idle Mode .................................................................. 108
Sleep Mode ............................................................... 108
Enabling and Disabling ............................................. 158
Operation .................................................................. 158
Timing Characteristics .............................................. 192
Timing Requirements ................................................ 193
Address Error Trap ............................................. 47
Math Error Trap................................................... 47
Oscillator Fail Trap.............................................. 48
Stack Error Trap.................................................. 48
© 2005 Microchip Technology Inc.