ACE1001MT8X Fairchild Semiconductor, ACE1001MT8X Datasheet - Page 19

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ACE1001MT8X

Manufacturer Part Number
ACE1001MT8X
Description
IC MCU 1KBIT EEPROM 8TSSOP
Manufacturer
Fairchild Semiconductor
Series
ACEX® 10xxr
Datasheet

Specifications of ACE1001MT8X

Core Processor
ACE1001
Core Size
8-Bit
Speed
4MHz
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (1K x 8)
Program Memory Type
EEPROM
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
ACE1001 Product Family Rev. B.1
5.0 Timer 1
Timer 1 is a versatile 8-bit timer. Its main function is to operate as
a Pulse Width Modulation (PWM) generator that generates pulses
of a specified width and duty cycles.
Timer 1 contains an 8-bit timer register (TMR1), an 8-bit auto-
reload register (T1RA), and an 8-bit control register (T1CNTRL).
All registers are memory-mapped for simple access through the
core. For the PWM signal generation the timer contains an output
(T1) that is multiplexed with the I/O pin G2.
The timer can be started or stopped through the T1CNTRL
register bit T1C0. When running, the timer counts down (decre-
ments) every clock cycle. The timer’s clock has a pre-scalar and
is selectable through two T1CNTRL register bits T1PSC[1:0].
Depending on the selected operating mode, occurrences of timer
Table 12: TIMER1 Control Register Bits
T1CNTRL Register
Bit 1,0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
-----------
-----------
Name
T1PND
T1PSC
T1EN
T1C1
T1C0
19
underflow (transitions from 0x00 to 0xFF or reload) can either
generate an interrupt and/or toggle the T1 output pin.
Timer 1’s interrupt (TMRI1) can be enabled by the interrupt enable
(T1EN) bit in the T1CNTRL register. When the timer interrupt is
enabled, the source of the interrupt is a timer underflow. By
default, the timer register is reset to 0xFF and the auto-reload
register is reset to 0x00.
5.1 Timer control bits
Reading and writing to the T1CNTRL register controls the timer’s
operation. By writing to the control bits, the user can enable or
disable the timer interrupts, set the mode of operation, start or stop
the timer, and select the clock. The T1CNTRL register bits are
described in Table 12.
Reserved
Reserved
T1 toggle enable bit: 1 = T1 toggle enabled, 0 = T1 toggle
disabled
TMR1 run: 1 = Start timer, 0 = Stop timer
Timer1 interrupt pending flag: 1 = Timer1 interrupt
pending, 0 = Timer1 interrupt not pending
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Pre-scalar selection bits: Selects the 1MHz clock divider to be
by 1 (00b), 2 (01b), 4 (10b), or 8 (11b)
Function
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