ATMEGA645-16AI Atmel, ATMEGA645-16AI Datasheet - Page 143

• Manufacturer Part Number: ATMEGA645-16AI
• Description: IC AVR MCU FLASH 64K 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

17.11 Register Description
17.11.1
2570M–AVR–04/11
TCCR2A – Timer/Counter Control Register A
For Timer/Counter2, the possible prescaled selections are: clk
clk
Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre-
dictable prescaler.
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare
match is forced on the Waveform Generation unit. The OC2A output is changed according to its
COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the
value present in the COM2A1:0 bits that determines the effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 17-2.
Note:
Bit
(0xB0)
Read/Write
Initial Value
Mode
T2S
0
1
2
3
/128, clk
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
135.
WGM21
(CTC2)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
FOC2A
T2S
Waveform Generation Mode Bit Description
W
7
0
/256, and clk
WGM20
(PWM2)
WGM20
0
1
0
1
R/W
6
0
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
T2S
COM2A1
R/W
5
0
/1024. Additionally, clk
COM2A0
R/W
4
0
ATmega325/3250/645/6450
WGM21
R/W
3
0
TOP
0xFF
0xFF
OCR2A
0xFF
T2S
CS22
R/W
Table 17-2
(1)
2
0
as well as 0 (stop) may be selected.
Update of
OCR2A at
Immediate
TOP
Immediate
BOTTOM
CS21
R/W
1
0
T2S
and
/8, clk
CS20
R/W
“Modes of Operation”
0
0
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
T2S
/32, clk
TCCR2A
T2S
/64,
143