ATMEGA6450-16AI Atmel, ATMEGA6450-16AI Datasheet - Page 190

• Manufacturer Part Number: ATMEGA6450-16AI
• Description: IC AVR MCU FLASH 64K 5V 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA6450-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2570M–AVR–04/11
Figure 20-4. Two-wire Mode Operation, Simplified Diagram
Figure 20-4
It is only the physical layer that is shown since the system operation is highly dependent of the
communication scheme used. The main differences between the Master and Slave operation at
this level, is the serial clock generation which is always done by the Master, and only the Slave
uses the clock control unit. Clock generation must be implemented in software, but the shift
operation is done automatically by both devices. Note that only clocking on negative edge for
shifting data is of practical use in this mode. The slave can insert wait states at start or end of
transfer by forcing the SCL clock low. This means that the Master must always check if the SCL
line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the
transfer is completed. The clock is generated by the master by toggling the USCK pin via the
PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-
bus, must be implemented to control the data flow.
Figure 20-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram (Figure 20-5.), a bus transfer involves the following steps:
SDA
SCL
SLAVE
MASTER
shows two USI units operating in Two-wire mode, one as Master and one as Slave.
Bit7
Bit7
A B
S
Bit6
Bit6
Bit5
Bit5
C
ADDRESS
1 - 7
Bit4
Bit4
Bit3
Bit3
R/W
8
Bit2
Bit2
D
Bit1
Bit1
ACK
9
Bit0
Bit0
E
ATmega325/3250/645/6450
DATA
1 - 8
Two-wire Clock
Control Unit
ACK
9
PORTxn
DATA
1 - 8
HOLD
SCL
SDA
SCL
SDA
SCL
ACK
9
VCC
P
F
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