PIC16CR73T-I/SS Microchip Technology, PIC16CR73T-I/SS Datasheet
PIC16CR73T-I/SS
Specifications of PIC16CR73T-I/SS
Related parts for PIC16CR73T-I/SS
PIC16CR73T-I/SS Summary of contents
Page 1
... Microchip Technology Inc. PIC16CR7X 28/40-Pin, 8-Bit CMOS ROM Microcontrollers Data Sheet DS21993C ...
Page 2
... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... PIC16CR76 8192 368 PIC16CR77 8192 368 © 2007 Microchip Technology Inc. PIC16CR7X Peripheral Features: • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep via external crystal/clock • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • ...
Page 4
... RA3/AN3/V REF 2 RA4/T0CKI PIC16CR73 3 RA5/AN4/SS 4 PIC16CR76 OSC1/CLKIN 6 7 OSC2/CLKOUT RB7 RB6 39 38 RB5 37 RB4 RB3 36 RB2 35 34 RB1 33 RB0/INT RD7/PSP7 29 RD6/PSP6 RD5/PSP5 28 RD4/PSP4 27 RC7/RX/DT 26 RC6/TX/CK 25 RC5/SDO 24 23 RC4/SDI/SDA RD3/PSP3 22 21 RD2/PSP2 RB3 20 RB2 19 RB1 18 RB0/INT RC7/RX/DT © 2007 Microchip Technology Inc. ...
Page 5
... Pin Diagrams (Continued) PLCC RA4/T0CKI RA5/AN4/SS RE0/AN5/RD RE1/AN6/WR RE2/AN7/ OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RB0/INT RB1 RB2 RB3 © 2007 Microchip Technology Inc. 39 RB3 7 38 RB2 8 37 RB1 9 36 RB0/INT 10 PIC16CR77 PIC16CR74 33 RD7/PSP7 13 32 RD6/PSP6 14 31 RD5/PSP5 ...
Page 6
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS21993C-page 4 © 2007 Microchip Technology Inc. ...
Page 7
... Capture/Compare/PWM Modules Serial Communications Parallel Communications 8-bit Analog-to-Digital Module Instruction Set Packaging © 2007 Microchip Technology Inc. The available features are summarized in Table 1-1. Block diagrams PIC16CR74/77 devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2 and Table 1-3. Additional information may be found in the “ ...
Page 8
... Serial Port Program ROM 4K 8K PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Data Memory 192 Bytes 368 Bytes © 2007 Microchip Technology Inc. ...
Page 9
... Timing Generation OSC1/CLKIN OSC2/CLKOUT MCLR Timer0 Timer1 CCP1 CCP2 Device PIC16CR74 PIC16CR77 Note 1: Higher order bits are from the STATUS register. © 2007 Microchip Technology Inc. 8 Data Bus Program Counter RAM 8-Level Stack File (13-bit) Registers (1) RAM Addr 9 Addr MUX Indirect 7 ...
Page 10
... External interrupt. I/O TTL Digital I/O. I/O TTL Digital I/O. I/O TTL Digital I/O. I/O TTL Digital I/O. I/O TTL Digital I/O. I/O TTL Digital I/O. I/O TTL Digital I/O. I/O = input/output P = power ST = Schmitt Trigger input Description © 2007 Microchip Technology Inc. ...
Page 11
... This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Verify mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. © 2007 Microchip Technology Inc. I/O/P Buffer Type Type PORTC is a bidirectional I/O port ...
Page 12
... Analog input 3. I A/D reference voltage input. ST I/O Digital I/O – Open drain when configured as output. I Timer0 external clock input. TTL I/O Digital I/O. I Analog input 4. I SPI slave select input. I/O = input/output P = power ST = Schmitt Trigger input Description © 2007 Microchip Technology Inc. ...
Page 13
... This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. © 2007 Microchip Technology Inc. I/O/P Buffer Type Type PORTB is a bidirectional I/O port ...
Page 14
... Chip Select control for parallel slave port . P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. — These pins are not internally connected. These pins should be left unconnected. I/O = input/output P = power ST = Schmitt Trigger input Description © 2007 Microchip Technology Inc. ...
Page 15
... Page 0 Page 1 On-Chip Program Memory Page 2 Page 3 © 2007 Microchip Technology Inc. 2.2 Data Memory Organization The Data Memory is partitioned into multiple banks, ® which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank ...
Page 16
... Purpose 118h 198h Register 119h 16 Bytes 199h 11Ah 19Ah 11Bh 19Bh 11Ch 19Ch 11Dh 19Dh 11Eh 19Eh 11Fh 19Fh 120h 1A0h General Purpose Register 80 Bytes 1EFh 16Fh 1F0h 170h accesses 70h-7Fh 17Fh 1FFh Bank 3 © 2007 Microchip Technology Inc. ...
Page 17
... General Purpose Register 96 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. * Not a physical register. Note 1: These registers are not implemented on 28-pin devices. © 2007 Microchip Technology Inc. File Address Indirect addr.(*) 80h TMR0 81h PCL PCL 82h STATUS ...
Page 18
... CCP1M1 CCP1M0 54, 96 --00 0000 OERR RX9D 70, 96 0000 -00x 75, 96 0000 0000 77, 96 0000 0000 58, 96 xxxx xxxx 58, 96 xxxx xxxx CCP2M1 CCP2M0 54, 96 --00 0000 88, 96 xxxx xxxx — ADON 83, 96 0000 00-0 © 2007 Microchip Technology Inc. ...
Page 19
... Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’. 6: This bit always reads as a ‘1’. © 2007 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE ...
Page 20
... DC C 19, 96 0001 1xxx 27, 96 xxxx xxxx — — 34, 96 1111 1111 — — — — — — 26, 96 ---0 0000 INTF RBIF 21, 96 0000 000x — RD 29, 97 1--- ---0 — 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...
Page 21
... For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. © 2007 Microchip Technology Inc. PIC16CR7X For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
Page 22
... To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 T0SE PSA PS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 128 R/W-1 R/W-1 PS1 PS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 23
... RBIF to be cleared least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state © 2007 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
Page 24
... PSPIE is reserved on 28-pin devices; always maintain this bit clear. DS21993C-page 22 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 25
... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Note 1: PSPIF is reserved on 28-pin devices; always maintain this bit clear. © 2007 Microchip Technology Inc. PIC16CR7X Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
Page 26
... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. U-0 U-0 U Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. U-0 R/W-0 — CCP2IE bit Bit is unknown U-0 R/W-0 ...
Page 27
... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) © 2007 Microchip Technology Inc. PIC16CR7X Note: BOR is unknown on POR. It must be set by the user and checked on subsequent Resets to see if BOR is clear, indicating a brown-out has occurred ...
Page 28
... ORG SUB1_P1 : : : RETURN contents of the PCLATH are CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 0x500 PCLATH,4 PCLATH,3 ;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) 0x900 ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to Call ;subroutine in page 0 ;(000h-7FFh) © 2007 Microchip Technology Inc. ...
Page 29
... Direct Addressing From Opcode RP1:RP0 6 Bank Select Location Select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail, see Figure 2-2. © 2007 Microchip Technology Inc. EXAMPLE 2-2: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE : 0 IRP Bank Select ...
Page 30
... PIC16CR7X NOTES: DS21993C-page 28 © 2007 Microchip Technology Inc. ...
Page 31
... RD: Read Control bit 1 = Initiates a ROM read cleared in hardware. The RD bit can only be set (not cleared) in software ROM read completed © 2007 Microchip Technology Inc. PIC16CR7X When interfacing to the program memory block, the PMDATH:PMDATA registers form a two-byte word, which holds ...
Page 32
... Address Register High Byte Data Register High Byte — — — — Value on Value on Bit 0 POR, all other BOR Resets xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — RD 1--- ---0 1--- ---0 © 2007 Microchip Technology Inc. ...
Page 33
... MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6>are always ; read as ‘0’. © 2007 Microchip Technology Inc. PIC16CR7X FIGURE 4-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Bus Port Q CK Data Latch ...
Page 34
... Input/output or slave select input for synchronous serial port or analog input. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 — — — PCFG2 PCFG1 PCFG0 Value on Value on all Bit 0 POR, other BOR Resets RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 ---- -000 ---- -000 © 2007 Microchip Technology Inc. ...
Page 35
... PORTB. The “mismatch” outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). © 2007 Microchip Technology Inc. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the ...
Page 36
... Bit 2 RB6 RB5 RB4 RB3 RB2 INTEDG T0CS T0SE PSA PS2 Value on Value on Bit 1 Bit 0 POR, all other BOR Resets RB1 RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS1 PS0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
Page 37
... Address Name Bit 7 Bit 6 07h PORTC RC7 RC6 87h TRISC PORTC Data Direction Register Legend unknown unchanged © 2007 Microchip Technology Inc. FIGURE 4-5: Port/Peripheral Select Peripheral Data Out Data Bus D WR Port Data Latch D WR TRIS TRIS Latch RD TRIS Peripheral ...
Page 38
... I/O PORT MODE (1) I/O pin CK Data Latch D Q Schmitt CK Trigger Input TRIS Latch Buffer and Function Value on Value on Bit 0 POR, all other BOR Resets RD0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 © 2007 Microchip Technology Inc. ...
Page 39
... Note Power-on Reset, these pins are configured as analog inputs and read as ‘0’. © 2007 Microchip Technology Inc. PIC16CR7X FIGURE 4-7: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) Data Bus ...
Page 40
... Bit 1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0 Bit 0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output DS21993C-page 38 R/W-0 U-0 R/W-1 PSPMODE — Bit Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 Bit 1 Bit 0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 41
... ADCON1 — — — Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. © 2007 Microchip Technology Inc. Function (1) Input/output port pin or read control input in Parallel Slave Port mode or analog input. For RD (PSP mode Idle 0 = Read operation ...
Page 42
... BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus Port CK TTL Port One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read Chip Select Write Note: I/O pin has protection diodes to V and V DD © 2007 Microchip Technology Inc. RDx pin TTL RD CS TTL WR TTL . SS ...
Page 43
... PSPIE 9Fh ADCON1 — — Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear. © 2007 Microchip Technology Inc ...
Page 44
... PIC16CR7X NOTES: DS21993C-page 42 © 2007 Microchip Technology Inc. ...
Page 45
... Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). © 2007 Microchip Technology Inc. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by ...
Page 46
... RC delay of 20 ns). Refer to the electrical specification of the desired device. R/W-1 R/W-1 R/W-1 T0SE PSA PS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared WDT Rate 128 R/W-1 R/W-1 PS1 PS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 47
... Legend unknown unchanged, © 2007 Microchip Technology Inc. value. The final 1:1 value is then set in lines 10 and 11 (highlighted). (Line numbers are included in the example for illustrative purposes only, and are not part of the actual code.) When assigned to the Timer0 module, all instructions writing to the TMR0 register (e ...
Page 48
... PIC16CR7X NOTES: DS21993C-page 46 © 2007 Microchip Technology Inc. ...
Page 49
... Internal clock (F OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). ...
Page 50
... The prescaler, however, will continue to increment. TMR1 TMR1L TMR1ON On/Off T1SYNC (2) 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock T1CKPS1:T1CKPS0 TMR1CS Synchronized 0 Clock Input 1 Synchronize det 2 Q Clock © 2007 Microchip Technology Inc. ...
Page 51
... TMR1L Read low byte MOVWF TMPL ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code © 2007 Microchip Technology Inc. PIC16CR7X 6.4.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware) ...
Page 52
... Value on Value on Bit 1 Bit 0 POR, all other BOR Resets INTF RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON --00 0000 --uu uuuu © 2007 Microchip Technology Inc. ...
Page 53
... Additional information on timer modules is available in ® the “PIC Mid-Range MCU Family Reference Manual” (DS33023). © 2007 Microchip Technology Inc. 7.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • ...
Page 54
... Bit 1 Bit 0 POR, all other BOR Resets 0000 000x 0000 000u INTF RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 -000 0000 -000 0000 T2CKPS0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
Page 55
... The rising edges are aligned. PWM Capture None. PWM Compare None. © 2007 Microchip Technology Inc. PIC16CR7X 8.2 CCP2 Module Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match ...
Page 56
... CCP1 clears Timer1; CCP2 clears Timer1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode DS21993C-page 54 R/W-0 R/W-0 R/W-0 CCPxY CCPxM3 CCPxM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CCPxM1 CCPxM0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 57
... The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode. © 2007 Microchip Technology Inc. 8.3.4 CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0 ...
Page 58
... TMR2IF TMR1IF 0000 0000 0000 0000 — CCP2IF ---- ---0 ---- ---0 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu © 2007 Microchip Technology Inc. ...
Page 59
... Reset Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 © 2007 Microchip Technology Inc. 8.5.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2 • 4 • T PWM frequency is defined [PWM period] ...
Page 60
... TMR1IE 0000 0000 0000 0000 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu © 2007 Microchip Technology Inc. ...
Page 61
... Refer to Application Note AN578, “Use of the SSP 2 Module in the I C™ Multi-Master Environment” (DS00578). © 2007 Microchip Technology Inc. 9.2 SPI Mode This section contains register definitions and opera- tional characteristics of the SPI module. Additional information on the SPI module can be found in the ® ...
Page 62
... Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS21993C-page 60 R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared C™ mode only) 2 C™ mode only) 2 C™ mode only) R-0 R-0 R-0 R bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 63
... C™ Firmware Controlled Master mode (slave Idle) 2 1110 = I C™ Slave mode, 7-bit address with Start and Stop bit interrupts enabled 2 1111 = I C™ Slave mode, 10-bit address with Start and Stop bit interrupts enabled © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
Page 64
... TRISC<5> bit (see Section 4.3 “PORTC and the TRISC Register” for information on instructions, such as BSF are performed on the TRISC register while the SS pin is high, this will cause the TRISC<5> bit to be set, thus disabling the SDO output PORTC). If Read-Modify-Write © 2007 Microchip Technology Inc. ...
Page 65
... SDI (SMP = 1) bit 7 SSPIF FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit 7 SDO SDI (SMP = 0) bit 7 SSPIF © 2007 Microchip Technology Inc. bit 6 bit 5 bit 4 bit 3 bit 6 bit 5 bit 3 bit 4 PIC16CR7X bit 2 bit 1 bit 0 ...
Page 66
... R/W UA bit 1 bit 0 bit 0 Value on Value on Bit 0 POR, all other BOR Resets RBIF 0000 000x 0000 000u 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 BF 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...
Page 67
... SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) – Not directly accessible • SSP Address Register (SSPADD) © 2007 Microchip Technology Inc. The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2 • ...
Page 68
... Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Generate ACK Pulse Yes Yes Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes © 2007 Microchip Technology Inc. ...
Page 69
... SDA signal is valid during the SCL high time (Figure 9-7). 2 FIGURE 9-7: I C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA SCL Data in sampled SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>) © 2007 Microchip Technology Inc. Receiving Data ACK ACK Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full ...
Page 70
... BOR Resets RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 BF 0000 0000 0000 0000 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
Page 71
... TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be parity bit © 2007 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous – Master (half duplex) • Synchronous – Slave (half duplex) Bit SPEN (RCSTA< ...
Page 72
... RX9D: 9th bit of Received Data Can be parity bit (parity to be calculated by firmware) DS21993C-page 70 R/W-0 U-0 R-0 CREN — FERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-x OERR RX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 73
... SPBRG Baud Rate Generator Register Legend unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2007 Microchip Technology Inc. It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the F OSC baud rate error in some cases ...
Page 74
... MHz OSC SPBRG % VALUE ERROR (DECIMAL) 1.73% 255 0.16% 64 -1.36% 32 1.73% 15 -1.36% 10 1.73% 7 -6.99% 6 8.51% 4 -16.67% 2 4.17 3.579545 MHz OSC SPBRG % VALUE ERROR (DECIMAL) 0.23% 185 0.23% 92 1.32% 22 -2.90% 11 -2.90% 5 -2.90% 3 -2.90% 2 16.52% 1 -2.90% 1 -10.51% 0 © 2007 Microchip Technology Inc. ...
Page 75
... TSR register is loaded. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. © 2007 Microchip Technology Inc. PIC16CR7X Note 1: The TSR register is not mapped in data memory not available to the user. ...
Page 76
... TX9D. 7. Load data to the TXREG register (starts transmission using interrupts, ensure that GIE and PEIE in the INTCON register are set. bit 0 bit 1 Word 1 Pin Buffer and Control RC6/TX/CK pin SPEN bit 7/8 Stop bit © 2007 Microchip Technology Inc. ...
Page 77
... Stop bit of the third byte, if the RCREG register is still full, the overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in © 2007 Microchip Technology Inc. bit 0 bit 1 Word 1 ...
Page 78
... If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PEIE in the INTCON register are set. FERR LSb • • • Start FIFO 8 Data Bus Start bit bit 7/8 Stop bit © 2007 Microchip Technology Inc. ...
Page 79
... Legend unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...
Page 80
... If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register using interrupts, ensure that GIE and PEIE in the INTCON register are set. © 2007 Microchip Technology Inc. ...
Page 81
... Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 bit 1 ...
Page 82
... RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PEIE in the INTCON register are set Q4Q1 Q4Q1 Q4Q1 bit 1 bit 2 bit 3 bit 4 bit bit 6 bit 7 ‘0’ © 2007 Microchip Technology Inc. ...
Page 83
... TSR and flag bit TXIF will now be set enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). © 2007 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TMR0IE ...
Page 84
... Value on Value on Bit 0 POR, all other BOR Resets RBIF 0000 000x 0000 000u 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...
Page 85
... A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Note: A/D channels 5, 6 and 7 are implemented on the PIC16CR74/77 only. © 2007 Microchip Technology Inc. The A/D module has three registers. These registers are: • A/D Result Register ((ADRES) • ...
Page 86
... U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared RA1 RA2 RA5 RA3 RE0 REF REF REF R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit Bit is unknown (1) (1) (1) RE1 RE2 V REF RA3 RA3 RA3 © 2007 Microchip Technology Inc. ...
Page 87
... Select an A/D input channel (ADCON0). FIGURE 11-1: A/D BLOCK DIAGRAM A/D Converter V REF (Reference Voltage) Note 1: Not available on PIC16CR73/76. © 2007 Microchip Technology Inc. 4. Wait for at least an appropriate acquisition period. 5. Start conversion: • Set GO/DONE bit (ADCON0) 6. Wait for the A/D conversion to complete, by either: • ...
Page 88
... Sampling Switch V = 0.6V T ≤ leakage V = 0.6V T ± 500 ADCS1:ADCS0 time of 4 μs but can vary between 2-6 μ see ACQ SS C HOLD = DAC Capacitance = 51 Sampling Switch (kΩ) Maximum Device Frequency Max. 1.25 MHz 5 MHz 20 MHz (Note 1) © 2007 Microchip Technology Inc. ...
Page 89
... Sleep whenever ADIF is set by hardware. In addition, an interrupt will also occur if the Global Interrupt bit GIE (INTCON<7>) is set. © 2007 Microchip Technology Inc. Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be changed and the ADIF flag will not be set ...
Page 90
... CCP2IF ---- ---0 ---- ---0 — CCP2IE ---- ---0 ---- ---0 xxxx xxxx uuuu uuuu — ADON 0000 00-0 0000 00-0 PCFG1 PCFG0 ---- -000 ---- -000 RA1 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 RE1 RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 © 2007 Microchip Technology Inc. ...
Page 91
... Reset while the power supply stabilizes, and is enabled or disabled, using a Configuration bit. With these two timers on-chip, most applications need no external Reset circuitry. © 2007 Microchip Technology Inc. PIC16CR7X Sleep mode is designed to offer a very low-current power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up or through an interrupt ...
Page 92
... The erased (unprogrammed) value of the Configuration Word is 3FFFh. DS21993C-page 90 (1) ) U-0 U-0 U-0 — — — R/P-1 R/P-1 R/P-1 CP0 PWRTEN WDTEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 7 R/P-1 R/P-1 FOSC1 FOSC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 93
... Table 12-1 and Table 12-2 recommended values of C1 and C2 series resistor (RS) may be required for AT strip cut crystals varies with the crystal chosen. © 2007 Microchip Technology Inc. FIGURE 12-2: Clock from Ext. System TABLE 12-1: Typical Capacitor Values Used: The Mode ...
Page 94
... R/C combination is connected to the PIC16CR7X FIGURE 12- EXT C EXT OSC Recommended values: ) values, and the operat- EXT values. The user also needs to EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC16CR7X OSC2/CLKOUT /4 3 kΩ ≤ R ≤ 100 kΩ EXT C > 20pF EXT © 2007 Microchip Technology Inc. ...
Page 95
... RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. © 2007 Microchip Technology Inc. PIC16CR7X Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” ...
Page 96
... Reset conditions for all the registers. to rise to an acceptable DD , parameter #33). PWRT falls below V DD BOR BOR falls below V for less DD BOR rises above V . The DD BOR should fall DD , the Brown-out Reset pro- rises above V , with the DD BOR © 2007 Microchip Technology Inc. ...
Page 97
... Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). © 2007 Microchip Technology Inc. bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. ...
Page 98
... Microchip Technology Inc. ...
Page 99
... See Table 12-5 for Reset value for specific condition. FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED NETWORK MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET © 2007 Microchip Technology Inc. Power-on Reset, MCLR Reset, Brown-out Reset WDT Reset 77 r000 0000 r000 0000 77 0000 0000 0000 0000 ...
Page 100
... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-9: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS21993C-page 98 T PWRT T PWRT THROUGH RC NETWORK PWRT T OST ): CASE OST ): CASE OST © 2007 Microchip Technology Inc. ...
Page 101
... TMR1IE CCP2IF CCP2IE Note 1: PSP interrupt is implemented only on PIC16CR74/77 devices. © 2007 Microchip Technology Inc. PIC16CR7X The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the Special Function Registers, PIR1 and PIR2 ...
Page 102
... PIC16CR76/77 devices, temporary holding regis- ters W_TEMP, STATUS_TEMP and PCLATH_TEMP should be placed in here. These 16 locations don’t require banking and, therefore, make it easier for context save and restore. The same code shown in Example 12-1 can be used. © 2007 Microchip Technology Inc. ...
Page 103
... RBPU Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of these bits. © 2007 Microchip Technology Inc. WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler), may be assigned using the OPTION_REG register ...
Page 104
... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. © 2007 Microchip Technology Inc. ...
Page 105
... PIC16CR7X microcontrollers are ROM-based, thus user programming is not possible. Please contact your Microchip sales representitive for details on how to submit your final code. This information can also be found in Application Note AN1010, “PIC16CR ROM Code Submission Process”. © 2007 Microchip Technology Inc (2) T OST Interrupt Latency ...
Page 106
... PIC16CR7X NOTES: DS21993C-page 104 © 2007 Microchip Technology Inc. ...
Page 107
... A read operation is performed on a register even if the instruction writes to that register. © 2007 Microchip Technology Inc. For example, a “CLRF PORTB” instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unin- ...
Page 108
... Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk ® Mid-Range MCU Family © 2007 Microchip Technology Inc. ...
Page 109
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. BCF k Syntax: Operands: Operation: Status Affected: ...
Page 110
... Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. ...
Page 111
... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2007 Microchip Technology Inc. PIC16CR7X INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 ≤ ...
Page 112
... Operation: TOS → PC Status Affected: None Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. ...
Page 113
... Carry Flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. C Register f © 2007 Microchip Technology Inc. PIC16CR7X SLEEP Syntax: [ label ] SLEEP Operands: None 00h → ...
Page 114
... Operation: Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. f,d ...
Page 115
... Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 116
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Advance Information ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
Page 117
... Microchip Technology Inc. 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 118
... Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. Advance Information ® L security ICs, CAN ® ® battery management, SEEVAL © 2007 Microchip Technology Inc. ...
Page 119
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. ........................................................................................... -0. )..................................................................................................................... ± ............................................................................................................. ± ...
Page 120
... PIC16CR7X FIGURE 15-1: PIC16CR7X VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V DS21993C-page 118 16 MHz 20 MHz Frequency © 2007 Microchip Technology Inc. ...
Page 121
... The Δ current is the additional current consumed when this peripheral is enabled. This current should be 6: added to the base When BOR is enabled, the device will operate correctly until the V © 2007 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T -40°C ≤ T Min Typ† Max Units 2.5 — ...
Page 122
... WDT enabled, -40°C to +85°C = 3.0V, WDT disabled, -40°C to +85°C = 4.0V, WDT enabled, -40°C to +85°C = 4.0V, WDT disabled, -40°C to +85°C = 4.0V, WDT enabled, -40° 4.0V, WDT disabled, -40° 5. and voltage trip point is reached. © 2007 Microchip Technology Inc. ...
Page 123
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2007 Microchip Technology Inc. PIC16CR7X Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature A -40° ...
Page 124
... V RA4 pin — — XT, HS and LP modes when external clock is used to drive OSC1 — — — — 400 pF © 2007 Microchip Technology Inc. ≤ +85°C for industrial ≤ +125°C for extended Conditions = 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V, DD ...
Page 125
... Load Condition 1 Pin Legend 464Ω for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16CR73/76 devices. © 2007 Microchip Technology Inc C™ specifications only C™ specifications only) T ...
Page 126
... LP osc mode ns XT osc mode ns HS osc mode ms LP osc mode ns RC osc mode ns XT osc mode ns HS osc mode ms LP osc mode 4/F CY OSC ns XT oscillator ms LP oscillator ns HS oscillator ns XT oscillator ns LP oscillator ns HS oscillator © 2007 Microchip Technology Inc. ...
Page 127
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKOUT output © 2007 Microchip Technology Inc ...
Page 128
... V — 1024 T — — T OSC 28 72 132 ms V μs — — 2.1 μs 100 — — V © 2007 Microchip Technology Inc. 34 Conditions = 5V, -40°C to +85° 5V, -40°C to +85° OSC1 period OSC = 5V, -40°C to +85°C DD ≤ V (D005) DD BOR ...
Page 129
... TCKEZtmr1 Delay from External Clock Edge to Timer Increment * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. PIC16CR7X ...
Page 130
... CY Standard(5V) 10 Extended(3V Standard(5V) 10 Extended(3V — Extended(3V) — Standard(5V) — Extended(3V) — Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value (1 © 2007 Microchip Technology Inc. ...
Page 131
... RD↑ or CS↓ to data out invalid * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. 65 Characteristic Min Typ† Max Units 20 ...
Page 132
... FIGURE 15-11: SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb In 74 Note: Refer to Figure 15-2 for load conditions. DS21993C-page 130 MSb Bit 75, 76 Bit Bit LSb 75, 76 Bit LSb LSb LSb © 2007 Microchip Technology Inc. ...
Page 133
... Note: Refer to Figure 15-2 for load conditions. FIGURE 15-13: SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI MSb In 74 Note: Refer to Figure 15-2 for load conditions. © 2007 Microchip Technology Inc MSb Bit 75, 76 MSb In Bit Bit LSb 75, 76 Bit LSb In ...
Page 134
... Extended(3V) — — Standard(5V) — Extended(3V) — Tcy — 1.5T CY Typ† Max Units Conditions — — — — — — ns — — ns — — — — — 145 ns — — ns — — — Stop Condition © 2007 Microchip Technology Inc. ...
Page 135
... I C™ BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 15-2 for load conditions. © 2007 Microchip Technology Inc. Min Typ Max Units 100 kHz mode 4700 — — 400 kHz mode 600 — — 100 kHz mode 4000 — ...
Page 136
... Repeated Start μs condition μs After this period the first clock pulse is generated μs ns μs ns (Note 2) ns μs μs ns (Note 1) ns μs Time the bus must be free before a new transmission μs can start bus system, but the © 2007 Microchip Technology Inc. ...
Page 137
... Data setup before CK↓ (DT setup time) 126 TckL2dtl Data hold after CK↓ (DT hold time) † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. 121 Characteristic Standard(5V) Extended(3V) Standard(5V) ...
Page 138
... REF DD ≤ V ≤ AIN REF ≤ V ≤ V — AIN REF V -40°C to +125°C V 0°C to +125°C V kΩ μA Average current consumption when A (Note 1). μA During V acquisition. AIN μA During A/D Conversion cycle. © 2007 Microchip Technology Inc. ...
Page 139
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 11.1 “A/D Acquisition Requirements” for minimum conditions. © 2007 Microchip Technology Inc. (1) 131 130 7 6 ...
Page 140
... PIC16CR7X NOTES: DS21993C-page 138 © 2007 Microchip Technology Inc. ...
Page 141
... FIGURE 16-2: MAXIMUM Typical: statistical mean @ 25°C 7 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125° 2. © 2007 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD 3.5V 3. Fosc(MHz) vs. F OVER V (HS MODE) OSC DD 3.5V 3.0V 10 ...
Page 142
... F OVER V (XT MODE) OSC DD 2 2.5 Fosc (MHz) vs. F OVER V (XT MODE) OSC DD 2 2.5 Fosc (MHz) 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3 3.5 4 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3 3.5 4 © 2007 Microchip Technology Inc. ...
Page 143
... FIGURE 16-6: MAXIMUM Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) 55 Minimum: mean – 3σ (-40°C to 125° © 2007 Microchip Technology Inc. VS. F OVER V (LP MODE) OSC Fosc (KHz) vs. F OVER V (LP MODE) OSC Fosc (KHz) PIC16CR7X 5.5V 5 ...
Page 144
... DS21993C-page 142 vs. V FOR VARIOUS VALUES Operation above 4 MHz is not recommended 10 kΩ 100 kΩ 3.5 4 4.5 VDD (V) vs. V FOR VARIOUS VALUES 5.1 kΩ 10 kΩ 100 kΩ 3.5 4 4.5 VDD (V) 5 5.5 5 5.5 © 2007 Microchip Technology Inc. ...
Page 145
... Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 0.01 2.0 2.5 © 2007 Microchip Technology Inc. vs. V FOR VARIOUS VALUES 3.5 4 Vdd (V) Max 125°C Max 85°C Typ 25°C 3 ...
Page 146
... DS21993C-page 144 OVER TEMPERATURE Indeterminant State 3.0 3.5 4.0 V (V) DD vs. V OVER TEMPERATURE WDT DD Max (125˚C) Typ (25˚C) 3.0 3.5 4.0 V (V) DD Device in SLEEP Max (125˚C) Typ (25˚C) 4.5 5.0 5.5 4.5 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 147
... FIGURE 16-14: AVERAGE WDT PERIOD vs 125°C 35 85°C 30 25° -40° 2.0 2.5 © 2007 Microchip Technology Inc. (125°C) Typ (25°C) (-40°C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (-40°C TO 125°C) DD 3.0 3.5 4.0 V (V) DD PIC16CR7X (-40°C TO 125°C) ...
Page 148
... DS21993C-page 146 vs (-mA Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Max Typ (25°C) Min (-mA 5V, -40°C TO 125°C) DD Max Typ (25°C) Min 3V, -40°C TO 125° © 2007 Microchip Technology Inc. ...
Page 149
... TYPICAL, MINIMUM AND MAXIMUM V 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 2.0 1.5 1.0 0.5 0 © 2007 Microchip Technology Inc. PIC16CR7X vs 5V, -40°C TO 125° Typ (25°C) Min (-40° ...
Page 150
... Max (-40° Typ (25° Min (125°C) TH 3.0 3.5 4.0 V (V) DD vs. V (ST INPUT, -40°C TO 125° 3.5 4.0 V (V) DD 4.5 5.0 5.5 Max (125°C) IH Min (-40° Max (-40° Min (125°C) IL 4.5 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 151
... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. PIC16CR7X Example e PICXXFXXXX-I/P ...
Page 152
... SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS21993C-page 150 Example XXFXXX e /ML 3 0710017 Example e 3 PICXXFXXXX/SO 0710017 Example PICXXFXXXX e -I/SS 3 0710017 Example PICXXFXXXX e 3 -I/PT 0710017 © 2007 Microchip Technology Inc. ...
Page 153
... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. © 2007 Microchip Technology Inc ...
Page 154
... A1 .015 – E .590 – E1 .485 – D 1.980 – L .115 – c .008 – b1 .030 – b .014 – eB – – Microchip Technology Drawing C04-016B MAX .250 .195 – .625 .580 2.095 .200 .015 .070 .023 .700 © 2007 Microchip Technology Inc. ...
Page 155
... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. © 2007 Microchip Technology Inc. CH2 x 45° CH1 x 45° ...
Page 156
... N e 0.65 BSC A 0.80 A1 0.00 A3 0.20 REF E 6.00 BSC E2 3.65 D 6.00 BSC D2 3.65 b 0.23 L 0. NOM MAX 28 0.90 1.00 0.02 0.05 3.70 4.20 3.70 4.20 0.30 0.35 0.55 0.70 – – Microchip Technology Drawing C04-105B © 2007 Microchip Technology Inc. ...
Page 157
... Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc α ...
Page 158
... A1 0.05 – E 7.40 7.80 E1 5.00 5.30 D 9.90 10.20 L 0.55 0.75 L1 1.25 REF c 0.09 – φ 0° 4° b 0.22 – Microchip Technology Drawing C04-073B φ L MAX 2.00 1.85 – 8.20 5.60 10.50 0.95 0.25 8° 0.38 © 2007 Microchip Technology Inc. ...
Page 159
... Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc ...
Page 160
... PIC16CR7X NOTES: DS21993C-page 158 © 2007 Microchip Technology Inc. ...
Page 161
... Data Memory (bytes) I/O Ports A/D Parallel Slave Port Interrupt Sources Packages © 2007 Microchip Technology Inc. Revision C (January 2007) This revision includes updates to the packaging diagrams. APPENDIX B: The differences between the devices in this data sheet are listed in Table B-1. ...
Page 162
... PSP, USART, SSP 2 (SPI Master/Slave) (SPI MHz 10-bit 2 4K, 8K FLASH (1,000 E/W cycles) (100 E/W cycles, typical) 192, 368 bytes 192, 368 bytes 128, 256 bytes In-Circuit Debugger, Low-Voltage Programming © 2007 Microchip Technology Inc. PIC16F7X 28/ Slave) 20 MHz 8-bit 2 4K, 8K FLASH None — ...
Page 163
... RA4/T0CKI Pin ................................................... 31 PORTB RB3:RB0 Port Pins ............................................. 33 RB7:RB4 Port Pins ............................................. 33 PORTC (Peripheral Output Override) ......................... 35 PORTD (In I/O Port Mode).......................................... 36 PORTD and PORTE (Parallel Slave Port) .................. 40 © 2007 Microchip Technology Inc. PORTE (In I/O Port Mode) ......................................... 37 PWM Mode................................................................. 57 RC Oscillator Mode .................................................... 92 Recommended MCLR Circuit..................................... 94 Reset Circuit ............................................................... 93 2 SSP (I C Mode) ...
Page 164
... Operation and ESD Protection ................................... 94 MCLR Pin ........................................................................... 10 MCLR/V Pin ...................................................................... 8 PP Memory Organization ......................................................... 13 Data Memory .............................................................. 13 Program Memory ........................................................ 13 Program Memory and Stack Maps ............................. 13 Microchip Internet Web Site.............................................. 167 MPLAB ASM30 Assembler, Linker, Librarian ................... 114 MPLAB ICD 2 In-Circuit Debugger ................................... 115 © 2007 Microchip Technology Inc. ...
Page 165
... POP .................................................................................... 26 POR. See Power-on Reset PORTA............................................................................ 8, 10 Analog Port Pins ..................................................... 8, 10 Associated Registers .................................................. 32 PORTA Register ......................................................... 31 RA4/T0CKI Pin........................................................ 8, 10 RA5/SS/AN4 Pin ..................................................... 8, 10 © 2007 Microchip Technology Inc. PIC16CR7X TRISA Register........................................................... 31 PORTA Register ................................................................. 31 PORTB ........................................................................... 8, 11 Associated Registers.................................................. 34 PORTB Register......................................................... 33 Pull-up Enable (RBPU Bit).......................................... 20 RB0/INT Edge Select (INTEDG Bit) ...
Page 166
... Associated Registers .................................................. 64 Serial Clock (SCK pin) ................................................ 59 Serial Data In (SDI pin)............................................... 59 Serial Data Out (SDO pin) .......................................... 59 Slave Select................................................................ 59 SSP Overview RA5/SS/AN4 Pin..................................................... 8, 10 RC3/SCK/SCL Pin .................................................. 9, 11 RC4/SDI/SDA Pin ................................................... 9, 11 RC5/SDO Pin.......................................................... SSP I C Operation.............................................................. 65 Slave Mode................................................................. 65 SSPEN bit........................................................................... 61 © 2007 Microchip Technology Inc. ...
Page 167
... Prescaler and Postscaler ............................................ 51 Timing Diagrams A/D Conversion......................................................... 137 Brown-out Reset ....................................................... 126 Capture/Compare/PWM (CCP1 and CCP2) ............. 128 CLKOUT and I/O....................................................... 125 External Clock........................................................... 124 Bus Data ............................................................. 133 © 2007 Microchip Technology Inc. PIC16CR7X Bus Start/Stop Bits ............................................. 132 Reception (7-bit Address)..................................... Transmission (7-bit Address) ............................... 67 Parallel Slave Port ...
Page 168
... Enable (WDTE Bit) ................................................... 101 Postscaler. See Postscaler, WDT Programming Considerations ................................... 101 RC Oscillator............................................................. 101 Time-out Period ........................................................ 101 WDT Reset, Normal Operation....................... 93, 95, 96 WDT Reset, SLEEP........................................ 93, 95, 96 WCOL bit ............................................................................ 61 Write Collision Detect bit (WCOL) ...................................... 61 WWW Address ................................................................. 167 WWW, On-Line Support ....................................................... 4 © 2007 Microchip Technology Inc. ...
Page 169
... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
Page 170
... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21993C-page 168 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS21993C Advance Information © 2007 Microchip Technology Inc. ...
Page 171
... TQFP (Thin Quad Flatpack PLCC SO = SOIC SP = Skinny Plastic DIP P = PDIP Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) © 2007 Microchip Technology Inc. XXX Examples: Pattern (Industrial) (Extended) Note1 Wide Voltage Range 2: T TQFP Advance Information PIC16CR7X . = Standard Voltage Range = in tape and reel PLCC, and packages only ...
Page 172
... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...