ATMEGA1284P-MU Atmel, ATMEGA1284P-MU Datasheet - Page 317
![MCU AVR 128K ISP FLASH 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA1284P-MU
Manufacturer Part Number
ATMEGA1284P-MU
Description
MCU AVR 128K ISP FLASH 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
PEREGRIN
Quantity:
1 992
Part Number:
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Manufacturer:
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Quantity:
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Company:
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Manufacturer:
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Quantity:
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26.10.8
26.10.9
26.10.10 Programming Command Register
8272A–AVR–01/10
Reset Register
Programming Enable Register
The Reset Register is a Test Data Register used to reset the part during programming. It is
required to reset the part before entering Programming mode.
A high value in the Reset Register corresponds to pulling the external reset low. The part is reset
as long as there is a high value present in the Reset Register. Depending on the Fuse settings
for the clock options, the part will remain reset for a Reset Time-out period (refer to
Sources” on page
not latched, so the reset will take place immediately, as shown in
The Programming Enable Register is a 16-bit register. The contents of this register is compared
to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con-
tents of the register is equal to the programming enable signature, programming via the JTAG
port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when
leaving Programming mode.
Figure 26-14. Programming Enable Register
The Programming Command Register is a 15-bit register. This register is used to serially shift in
programming commands, and to serially shift out the result of the previous command, if any. The
JTAG Programming Instruction Set is shown in
when shifting in the programming commands is illustrated in
164A/164PA/324A/324PA/644A/644PA/1284/1284P
31) after releasing the Reset Register. The output from this Data Register is
TDO
TDI
D
A
A
T
0xA370
=
ClockDR & PROG_ENABLE
D
Table 26-18 on page
Q
Programming Enable
Figure 26-16 on page
Figure 24-2 on page
319. The state sequence
322.
269.
”Clock
317
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