ATMEGA324P-15AZ Atmel, ATMEGA324P-15AZ Datasheet - Page 210
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ATMEGA324P-15AZ
Manufacturer Part Number
ATMEGA324P-15AZ
Description
MCU AVR 32K FLASH 15MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA324P-15AZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.2.1
19.2.2
19.3
19.3.1
210
Data Transfer and Frame Format
ATmega164P/324P/644P
TWI Terminology
Electrical Interconnection
Transferring Bits
The following definitions are frequently encountered in this section.
Table 19-1.
The Power Reduction TWI bit, PRTWI bit in
be written to zero to enable the 2-wire Serial Interface.
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices trim-state their outputs, allowing the pull-up resistors to pull the
line high. Note that all AVR devices connected to the TWI bus must be powered in order to allow
any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
specifications are presented there, one relevant for bus speeds below 100 kHz, and one valid for
bus speeds up to 400 kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Term
Master
Slave
Transmitter
Receiver
TWI Terminology
Figure
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
19-1, both bus lines are connected to the positive supply voltage through
“SPI Timing Characteristics” on page
“PRR – Power Reduction Register” on page 47
333. Two different sets of
7674F–AVR–09/09
must
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