ATMEGA324P-15MT1 Atmel, ATMEGA324P-15MT1 Datasheet - Page 373
![MCU AVR 32K FLASH 15MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA324P-15MT1
Manufacturer Part Number
ATMEGA324P-15MT1
Description
MCU AVR 32K FLASH 15MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA324P-15MT1
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7674F–AVR–09/09
20 AC - Analog Comparator ..................................................................... 240
21 ADC - Analog-to-digital Converter ..................................................... 243
22 JTAG Interface and On-chip Debug System ..................................... 263
23 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 269
19.7
19.8
19.9
20.1
20.2
20.3
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
22.10
23.1
23.2
23.3
23.4
23.5
23.6
Transmission Modes .....................................................................................221
Multi-master Systems and Arbitration ............................................................234
Register Description ......................................................................................235
Overview ........................................................................................................240
Analog Comparator Multiplexed Input ...........................................................240
Register Description ......................................................................................241
Features ........................................................................................................243
Overview ........................................................................................................243
Operation .......................................................................................................244
Starting a Conversion ....................................................................................245
Prescaling and Conversion Timing ................................................................246
Changing Channel or Reference Selection ...................................................249
ADC Noise Canceler .....................................................................................251
ADC Conversion Result .................................................................................256
Register Description ......................................................................................258
Features ........................................................................................................263
Overview ........................................................................................................263
TAP – Test Access Port ................................................................................264
TAP Controller ...............................................................................................265
Using the Boundary-scan Chain ....................................................................266
Using the On-chip Debug System .................................................................266
On-chip Debug Specific JTAG Instructions ...................................................267
Using the JTAG Programming Capabilities ...................................................268
Bibliography ...................................................................................................268
Register Description ......................................................................................268
Features ........................................................................................................269
Overview ........................................................................................................269
Data Registers ...............................................................................................270
Boundary-scan Specific JTAG Instructions ...................................................271
Boundary-scan Chain ....................................................................................272
ATmega164P/324P/644P Boundary-scan Order ..........................................275
ATmega164P/324P/644P
373
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