ADUC824BS Analog Devices Inc, ADUC824BS Datasheet - Page 25

• Manufacturer Part Number: ADUC824BS
• Description: IC MCU 8K FLASH ADC/DAC 52MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC824BS

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 3x16b, 4x24b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SFR INTERFACE TO THE PRIMARY AND AUXILIARY
ADCS
Both ADCs are controlled and configured via a number of SFRs
that are mentioned here and described in more detail in the
following pages.
ADCSTAT:
ADCMODE: ADC Mode Register. Controls general modes
ADC0CON: Primary ADC Control Register. Controls
ADC1CON: Auxiliary ADC Control Register. Controls
SF:
ADCSTAT—(ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration and various (ADC-related) error and warning conditions
including reference detect and conversion overflow/underflow flags.
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
R
D
Y
0
ADC Status Register. Holds general status of
the Primary and Auxiliary ADCs.
of operation for Primary and Auxiliary ADCs.
specific configuration of Primary ADC.
specific configuration of Auxiliary ADC.
Sinc Filter Register. Configures the decimation
factor for the Sinc3 filter and thus the Primary
and Auxiliary ADC update rates.
Name
RDY0
RDY1
CAL
NOXREF
ERR0
ERR1
—
—
R
D
Y
1
Ready Bit for Auxiliary ADC
D8H
00H
Yes
Description
Ready Bit for Primary ADC
Set by hardware on completion of ADC conversion or calibration cycle.
Cleared directly by the user or indirectly by write to the mode bits to start another Primary
ADC conversion or calibration. The Primary ADC is inhibited from writing further results to its
data or calibration registers until the RDY0 bit is cleared.
Same definition as RDY0 referred to the Auxiliary ADC.
Calibration Status Bit
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
No External Reference Bit (only active if Primary or Auxiliary ADC is active).
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a
specified threshold. When Set conversion results are clamped to all ones,if using ext. reference.
Cleared to indicate valid V
Primary ADC Error Bit
Set by hardware to indicate that the result written to the Primary ADC data registers has
been clamped to all zeros or all ones. After a calibration this bit also flags error conditions that
caused the calibration registers not to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.
Auxiliary ADC Error Bit
Same definition as ERR0 referred to the Auxiliary ADC.
Reserved for Future Use
Reserved for Future Use
C
A
L
Table III. ADCSTAT SFR Bit Designations
N
O
X
R
E
F
REF
.
ICON:
ADC0L/M/H: Primary ADC 24-bit conversion result held in
ADC1L/H:
OF0L/M/H:
OF1L/H:
GN0L/M/H: Primary ADC 24-bit Gain Calibration Coefficient
GN1L/H:
E
R
R
0
Current Source Control Register. Allows user
control of the various on-chip current source
options.
these three 8-bit registers.
Auxiliary ADC 16-bit conversion result held
in these two 8-bit registers.
Primary ADC 24-bit Offset Calibration Coefficient
held in these three 8-bit registers.
Auxiliary ADC 16-bit Offset Calibration Coefficient
held in these two 8-bit registers.
held in these three 8-bit registers.
Auxiliary ADC 16-bit Gain Calibration Coefficient
held in these two 8-bit registers.
E
R
R
1
—
ADuC824
—