ADUC831BS-REEL Analog Devices Inc, ADUC831BS-REEL Datasheet - Page 30

• Manufacturer Part Number: ADUC831BS-REEL
• Description: IC MCU 62K FLASH ADC/DAC 52MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC831BS-REEL

• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• For Use With: EVAL-ADUC831QSZ - KIT DEV FOR ADUC831 QUICK START

ADuC831
Example: Programming the Flash/EE Data Memory
A user wishes to program F3H into the second byte on Page
03H of the Flash/EE data memory space while preserving the
other three bytes already in this page.
A typical program of the Flash/EE Data array will involve:
Step 1: Set Up the Page Address
The two address registers EADRH and EADRL hold the high
byte address and the low byte address of the page to be
addressed. The assembly language to set up the address may
appear as:
Step 2: Set Up the EDATA Registers
We must now write the four values to be written into the page
into the four SFRs EDATA–14. Unfortunately, we do not know
three of them. Thus, we must read the current page and over-
write the second byte.
Step 3: Program Page
A byte in the Flash/EE array can only be programmed if it has
previously been erased. To be more specific, a byte can only be
programmed if it already holds the value FFH. Because of the
Flash/EE architecture, this erase must happen at a page level;
therefore, a minimum of four bytes (one page) will be erased
when an erase command is initiated. Once the page is erased we
can program the four bytes in-page and then perform a verification
of the data.
Although the 4 kBytes of Flash/EE data memory are shipped
from the factory pre-erased, i.e., byte locations set to FFH, it is
nonetheless good programming practice to include an erase-all
routine as part of any configuration/setup code running on the
ADuC831. An “ERASE-ALL” command consists of writing
“06H” to the ECON SFR, which initiates an erase of the
4 kByte Flash/EE array. This command coded in 8051 assembly
would appear as:
MOV EADRH,#0
MOV EADRL,#03H
MOV ECON,#1
MOV EDATA2,#0F3H
MOV ECON,#5
MOV ECON,#2
MOV ECON,#4
MOV A,ECON
JNZ ERROR
MOV ECON,#06H
1) setting EADRH/L with the page address
2) writing the data to be programmed to the EDATA1–4
3) writing the ECON SFR with the appropriate command
; Set Page Address Pointer
; Read Page into EDATA1-4
; Overwrite byte 2
; Erase all Command
; 2 ms Duration
; ERASE Page
; WRITE Page
; VERIFY Page
; Check if ECON=0 (OK!)
–30–
Flash/EE Memory Timing
Typical program and erase times for the ADuC831 are as
follows:
NORMAL MODE (operating on Flash/EE data memory)
ULOAD MODE (operating on Flash/EE program memory)
It should be noted that a given mode of operation is initiated as
soon as the command word is written to the ECON SFR. The
core microcontroller operation on the ADuC831 is idled until the
requested Program/Read or Erase mode is completed.
In practice, this means that even though the Flash/EE memory
mode of operation is typically initiated with a two-machine cycle
MOV instruction (to write to the ECON SFR), the next instruc-
tion will not be executed until the Flash/EE operation is complete.
This means that the core will not respond to interrupt requests
until the Flash/EE operation is complete, although the core
peripheral functions like counter/timers will continue to count
and time as configured throughout this period.
READPAGE (4 bytes)
WRITEPAGE (4 bytes)
VERIFYPAGE (4 bytes)
ERASEPAGE (4 bytes)
ERASEALL (4 kBytes)
READBYTE (1 byte)
WRITEBYTE (1 byte)
WRITEPAGE (256 bytes)
ERASEPAGE (64 bytes)
ERASEALL (56 kBytes)
WRITEBYTE (1 byte)
– 5 machine cycles
– 380 µs
– 5 machine cycles
– 2 ms
– 2 ms
– 3 machine cycle
– 200 µs
– 15 ms
– 2 ms
– 2 ms
– 200 µs
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