Z86E4312VSC Zilog, Z86E4312VSC Datasheet - Page 42

• Manufacturer Part Number: Z86E4312VSC
• Description: IC MICROCONTROLLER 4K 44-PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E4312VSC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• For Use With: 309-1042 - ADAPTER 44-PLCC ZIF TO 44-PLCC309-1041 - ADAPTER 44-PLCC TO 44-PLCC309-1038 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1037 - ADAPTER 44-PLCC TO 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-1038

PS022901-0508
Application Precaution
Standard Mode
CLR Clear (active High). This pin resets the internal address counter at the High Level.
CLK Address Clock. This pin is a clock input. The internal address counter increases by
one for each clock cycle.
The production test-mode environment may be enabled accidentally during normal opera-
tion if excessive noise surges above V
In addition, processor operation of Z8 OTP devices may be affected by excessive noise
surges on the V
Recommendations for dampening voltage surges in both test and OTP mode include the
following:
•
•
•
XTAL Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic
resonator, LC, RC network, or external single-phase clock to the on-chip oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant crystal,
ceramic resonator, LC, or RC network to the on-chip oscillator output.
R/W Read/Write (output, write Low). The R/W signal is Low when the CCP is writing to
the external program or data memory (Z86E43/743/E44 only).
RESET Reset (input, active Low). Reset will initialize the MCU. Reset is accomplished
either through Power-On, Watchdog Timer reset, Stop Mode Recovery, or external reset.
During Power-On Reset and Watchdog Timer Reset, the internally generated reset drives
the reset pin low for the POR time. Any devices driving the reset line must be open-drain
in order to avoid damage from a possible conflict during reset conditions. Pull-up is pro-
vided internally. After the POR time, RESET is a Schmitt-triggered input. (RESET is
available on Z86E43/743/E44 only.)
To avoid asynchronous and noisy reset problems, the Z86E43/743/E44 is equipped with a
reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in
duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST sig-
nal is latched and held for an internal register count of 18 external clocks, or for the dura-
tion of the external reset, whichever is longer. During the reset cycle, DS is held active
Low while AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 5-
10 TpC cycles after RESET is released. For Power-On Reset, the reset output time is 5 ms.
Using a clamping diode to V
Adding a capacitor to the affected pin
Enable EPROM/Test Mode Disable OTP option bit.
PP
, EPM, OE pins while the microcontroller is in Standard Mode.
CC
CC
occur on pins P31 and RESET.
CMOS Z8
®
Product Specification
OTP Microcontrollers
Electrical Characteristics
38