SX28AC/DP-G Parallax Inc, SX28AC/DP-G Datasheet - Page 20

• Manufacturer Part Number: SX28AC/DP-G
• Description: IC MCU 2K FLASH 50MHZ 28DIP
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX28AC/DP-G

• Core Size: 8-Bit
• Program Memory Size: 3KB (2K x 12)
• Oscillator Type: Internal
• Core Processor: RISC
• Speed: 75MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 20
• Program Memory Type: FLASH
• Ram Size: 136 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: SX
• No. Of I/o's: 20
• Eeprom Memory Size: 2048Byte
• Ram Memory Size: 136Byte
• Cpu Speed: 75MHz
• Processor Series: Ubicom SXx
• Core: RISC
• Data Bus Width: 8 bit
• Data Ram Size: 136 B
• Maximum Clock Frequency: 75 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: 32300, 28138, 45302
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: SX28AC/DP; SX28AC/DP

Parallax SX20AC/SX28AC
7.2.
The WKPND_B register comes up with an unknown
value upon reset. The user program must clear the register
prior to enabling the wake-up condition or interrupts. The
proper initialization sequence is:
Below is an example of how to read the WKPND_B
register to determine which Port B pin caused the wakeup
or interrupt, and to clear the WKPND_B register:
mov
clr
mov
The final “mov” instruction in this example performs an
exchange of data between the working register (W) and
the WKPND_B register. This exchange occurs only with
Port B accesses. Otherwise, the “mov” instruction does
not perform an exchange, but only moves data from the
source to the destination.
© Parallax Inc.
1. Select the desired edge (through WKED_B
2. Clear the WKPND_B register.
3. Enable
Port B MIWU/Interrupt Configuration
register).
WKEN_B register).
M,#$09
W
RB,W
;W contains WKPND_B
;contents of W exchanged
;with contents of WKPND_B
the
Wakeup
condition
(through
Page 20 of 51
Here is an example of a program segment that configures
the RB0, RB1, and RB2 pins to operate as Multi Input
Wakeup/Interrupt pins, sensitive to falling edges:
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
To prevent false interrupts, the enabling step (clearing bits
in WKEN_B) should be done as the last step in a
sequence of Port B configuration steps. After this
program segment is executed, the device can receive
interrupts on the RB0, RB1, and RB2 pins. If the device is
put into the power down mode (by executing the SLEEP
instruction), the device can then receive wakeup signals
on those same pins.
M,#$0F ;prepare to write port data
W,#$07 ;load W with the value 07h
RB,W
M,#$0A ;prepare to write WKED_B
!RB,W
M,#$09 ;prepare to access WKPND_B
W,#$00 ;clear W
!RB,W
M,#$0B ;prepare to write WKEN_B (enable)
W,#$F8h ;load W with the value F8h
!RB,W
;direction registers
;configure RB0-RB2 to be inputs
;(edge) register
;W contains the value 07h
;configure RB0-RB2 to sense
;falling edges
;(pending) register
;clear all wakeup pending bits
;register
;enable RB0-RB2 to operate as
;wakeup inputs
Rev 1.6 11/20/2006
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