CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 109

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CY8C26643-24AI

Manufacturer Part Number
CY8C26643-24AI
Description
IC MCU 16K FLASH 256B 44LQFP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet

Specifications of CY8C26643-24AI

Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
428-1431
428-1431-5
428-1431

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Table 84:
Multiply Result High Register (MUL_DH, Address = Bank 0, EAh)
Table 85:
Multiply Result Low Register (MUL_DL, Address = Bank 0, EBh)
Table 86:
Accumulator Result 1 / Multiply/Accumulator Input X Register (ACC_DR1 / MAC_X, Address = Bank 0, ECh)
Table 87:
Accumulator Result 0 / Multiply/Accumulator Input Y Register (ACC_DR0 / MAC_Y, Address = Bank 0, EDh)
September 5, 2002
Bit [7:0] : Data [7:0] 8-bit data value is the high order result of the multiply function
Bit [7:0] : Data [7:0] 8-bit data value is the low order result of the multiply function
Bit [7:0] : Data [7:0]
8-bit data value when read is the next to lowest order result of the multiply/accumulate function
8-bit data value when written is the X multiplier input to the multiply/accumulate function
Bit [7:0] : Data [7:0]
8-bit data value when read is the lowest order result of the multiply/accumulate function
8-bit data value when written is the Y multiplier input to the multiply/accumulate function
Read/Write
Read/Write
Read/Write
Read/Write
Bit Name
Bit Name
Bit Name
Bit Name
Bit #
POR
Bit #
POR
Bit #
POR
Bit #
POR
Multiply Result High Register
Multiply Result Low Register
Accumulator Result 1 / Multiply/Accumulator Input X Register
Accumulator Result 0 / Multiply/Accumulator Input Y Register
Data [7]
Data [7]
Data [7]
Data [7]
RW
RW
R
R
7
0
7
0
7
0
7
0
Data [6]
Data [6]
Data [6]
Data [6]
R
R
RW
6
0
6
0
RW
6
0
6
0
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Data [5]
Data [5]
Data [5]
Data [5]
RW
R
R
5
0
5
0
5
0
RW
5
0
Data [4]
Data [4]
Data [4]
Data [4]
RW
R
4
0
R
4
0
4
0
RW
4
0
Data [3]
Data [3]
Data [3]
Data [3]
RW
R
3
0
3
0
RW
R
3
0
3
0
Data [2]
Data [2]
Data [2]
Data [2]
RW
RW
R
2
0
2
0
2
0
R
2
0
Special Features of the CPU
Data [1]
Data [1]
Data [1]
Data [1]
RW
R
RW
1
0
1
0
1
0
R
1
0
Data [0]
Data [0]
Data [0]
Data [0]
RW
RW
R
0
0
0
0
0
0
R
0
0
109

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