Z8F4802VS020SC Zilog, Z8F4802VS020SC Datasheet - Page 6

• Manufacturer Part Number: Z8F4802VS020SC
• Description: IC ENCORE MCU FLASH 48K 68-PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F4802VS020SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 269-3146

Table 1. Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x Errata for Devices with Date
UP004207-0308
Sl
No
18
19
20
Summary
When receiving
data, the IrDA endec
may have bit errors
if the external
transmitter’s baud
rate is greater than
endec baud rate.
When the CPU exits
from HALT mode, it
fails to reset the
master Interrupt
Request Enable
(IRQE) bit.
The DMA does not
support the ADC in
CONTINUOUS
mode.
Codes 0239 and Later (Continued)
Errata to Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x (Z8 Encore!
Description
The IrDA endec is sensitive to external transmitters that have baud rates
somewhat higher than the baud rate of the Z8F640x, Z8F480x, Z8F320x,
Z8F240x, Z8F160x’s endec. This can cause bit errors in the data
transmission.
Workaround
When receiving, increase the baud rate of the UART and IrDA endec by a few
percent. The endec can handle minor baud rate discrepancies to an external
transmitter that is slower, but is sensitive to an external transmitter that is
faster. When the endec is transmitting, the baud rate should be set as close as
possible to the desired baud rate.
When the CPU exits from HALT mode, it fails to reset the master Interrupt
Request Enable (IRQE) bit (bit 7 of the Interrupt Control Register).
Watchdog Timer (WDT) interrupts will cause the Program Counter (PC) and
Flags to be pushed twice on the stack. The first push will be the PC and Flags
from where the interrupt occurred. The second push will be the starting
address and Flags of the ISR.
This problem also affects exits from HALT mode caused by other interrupt
sources if more than one interrupt is pending. If only a single interrupt is
pending then the routine is executed normally except that interrupts are not
disabled.
Workaround
To mimic standard interrupt operation, the ISR should execute a Disable Inter-
rupts (DI) instruction to reset the Master Interrupt Request Enable (IRQE) bit
to 0.
Further, on WDT interrupts before exiting, the ISR should add three to the
Stack Pointer (SP). On Normal interrupts the ISR should check the PC on the
stack. If the PC on the stack contains the starting address of the ISR, then the
ISR should add three to the SP. This problem only affects exits from HALT
mode.
The DMA does not support the ADC in CONTINUOUS mode.
Workaround
None.
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