LH75410N0M100C0 Sharp Microelectronics, LH75410N0M100C0 Datasheet - Page 60
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LH75410N0M100C0
Manufacturer Part Number
LH75410N0M100C0
Description
IC ARM7 BLUESTREAK MCU 144TQFP
Manufacturer
Sharp Microelectronics
Series
BlueStreak ; LH7r
Specifications of LH75410N0M100C0
Core Processor
ARM7
Core Size
16/32-Bit
Speed
84MHz
Connectivity
EBI/EMI, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
425-1862
LH75410N0M100
SM75410C0-M-100-30
LH75410N0M100
SM75410C0-M-100-30
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH75410N0M100C0
Manufacturer:
Sharp Microelectronics
Quantity:
10 000
LH75400/01/10/11
Analog-To-Digital Converter Electrical
Characteristics
extended temperature operation. See Figure 11 for the
ADC transfer characteristics.
NOTES:
1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion,
2. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer,
3. The analog input pins can be driven anywhere between the power supply rails. If the voltage at the input to the
4. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down.
60
A/D Resolution
Throughput Conversion
Acquisition Time
Clk Frequency
Differential Non-Linearity
Integral Non-Linearity
Offset Error
Gain Error
On-chip Voltage Reference (VREF)
Negative Reference Input (VREF-)
Positive Reference Input (VREF+)
Crosstalk between channels
Analog Input Voltage Range
Analog Input Current
Reference Input Current
Analog input capacitance
Operating Supply Voltage
Operating Current, VDDA
Standby Current
Stop Current, VDDA
Brown Out Trip Point
Brown Out Hysterisis
Operating Temperature
Table 25 shows the derated specifications for
plus 1 × A2DCLK cycles to be made available in the PCLK domain.
An additional 3 × PCLK cycles are required before being available on the APB.
alternative low impedance (RS < 500) voltages can be selected as reference voltages. The range of voltages
allowed are specified above. However, the on-chip reference cannot drive the ADC unless the reference buffer is switched on.
ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale.
Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be
forward-biased, resulting in large current source/sink and possible damage to the ADC.
PARAMETER
Table 25. ADC Electrical Characteristics at Industrial Operating Range
(VREF-) +1.0
VSSA
-0.99
MIN.
1.85
-3.5
-4.0
500
-35
3.0
-40
10
17
3
0
Version 1.2
VSSA
VREF
TYP.
2.63
590
180
120
-60
< 1
2.0
(VREF+) -1.0
VDDA
VDDA
MAX.
5,000
+3.5
2.15
+35
4.5
4.0
3.6
10
15
85
5
5
CLK Cycles
CLK Cycles
UNITS
LSB
LSB
LSB
Bits
mV
mV
dB
μA
μA
pF
μA
μA
μA
°C
ns
V
V
V
V
V
V
System-on-Chip
Data Sheet
NOTES
2
1
2
3
4