LH75400N0Q100C0 Sharp Microelectronics, LH75400N0Q100C0 Datasheet - Page 63
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LH75400N0Q100C0
Manufacturer Part Number
LH75400N0Q100C0
Description
IC ARM7 BLUESTREAK MCU 144LQFP
Manufacturer
Sharp Microelectronics
Series
BlueStreak ; LH7r
Specifications of LH75400N0Q100C0
Core Processor
ARM7
Core Size
16/32-Bit
Speed
84MHz
Connectivity
CAN, EBI/EMI, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH75400N0Q100C0
Manufacturer:
Sharp Microelectronics
Quantity:
10 000
System-on-Chip
AC Characteristics
point of the signal.
NOTE: The values in Table 28 represent the timing with no internal arbitration
Data Sheet
D[15:0]
D[15:0]
D[15:0]
nCS3 - nCS0
nCS3 -nCS0
nOE
nOE
nBLE1 - nBLE0 Out 30 pF
nBLE1 - nBLE0 Out 30 pF
nBLE1 - nBLE0 Out 30 pF
nWE
nWE
nWAIT
SSPFRM
SIGNAL
All signal transitions are measured from the 50%
SSPRX
SSPTX
PARAMETER
SIGNAL
tRSTOV
tOSC32
tOSC14
tPORH
tLREG
delay and 1 wait state memory access. This is the worst case (fastest) timing.
Out
Out
I/O
In
Out 50 pF
Out 50 pF
Out 30 pF
Out 30 pF
Out 30 pF
Out 30 pF
Out 30 pF
Out 30 pF
I/O LOAD PARAMETER
In
In
Linear regulator stabilization time after power-up
Oscillator stabilization time after Power Up (VDDC = VDDCMIN)
Oscillator stabilization time after Power Up (VDDC = VDDCMIN)
nPOR LOW to nPOR valid (once sampled LOW)
nPOR hold extend to allow PLL to lock once XTAL is stable
LOAD
50 pF
50 pF
PARAMETER
tOVSSPFRM
tOHBEW
tOHBER
tIVWAIT
tOVSSPTX
tOHWE
tOVWE
tOVCS
tOHCS
tOVOE
tOHOE
tOVBE
tOVD
tOHD
tISSPRX
tIDD
Table 28. Memory Interface Signals
Table 29. Synchronous Serial Port
Table 30. Power-up Stabilization
3 × tHCLK – 6 ns
3 × tHCLK – 6 ns
3 × tHCLK – 6 ns
3 × tHCLK – 6 ns
2 × tHCLK – 6 ns
2 × tHCLK – 6 ns 2 tHCLK – 2.2 ns nWE output invalid following address valid
DESCRIPTION
MINIMUM
22 ns
MIN.
Version 1.2
MAX.
14 ns SSPFRM output valid, referenced to SSPCLK
12 ns SSPTX output valid, referenced to SSPCLK
2 tHCLK – 18 ns nWAIT input valid following address valid
2 tHCLK – 18 ns Data input valid following address valid
2 × tHCLK – 18 ns
tHCLK + 10 ns
tHCLK + 10 ns
tHCLK + 10 ns
tHCLK + 8 ns
tHCLK + 6 ns
+ (nWAIT –1)
MAXIMUM
SSPRX input valid, referenced to SSPCLK
× tHCLK
Data output invalid following address valid
Data output valid following address valid
Data Input Valid, following
Address Valid (nWAIT states)
nCS output valid following address valid
nCS output invalid following address valid
nOE output valid following address valid
nOE output invalid following address valid
nBLE output valid following address valid
nBLE output invalid following address
valid, read cycle
nBLE output invalid following address
valid, write cycle
nWE output valid following address valid
COMMENT
COMMENTS
TYP.
3.5
LH75400/01/10/11
MAX.
200
550
2.5
10
HCLK
UNIT
ms
ms
μs
μs
63