C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 42
C8051F321R
Manufacturer Part Number
C8051F321R
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet
1.C8051F320R.pdf
(256 pages)
Specifications of C8051F321R
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1067-2
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C8051F320/1
5.3.
ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system
clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for
0 ≤ AD0SC ≤ 31).
5.3.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of Conver-
sion Mode bits (AD0CM2-0) in register ADC0CN. Conversions may be initiated by one of the following:
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-demand".
During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The fall-
ing edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). Note: When
polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is avail-
able in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1. Note that when Timer 2 or Timer 3
overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte
overflows are used if Timer 2/3 is in 16-bit mode. See
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital Crossbar. To
configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See
page 127
42
Modes of Operation
1.
2.
3.
4.
5.
6.
for details on Port I/O configuration.
Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
A Timer 0 overflow (i.e., timed continuous conversions)
A Timer 2 overflow
A Timer 1 overflow
A rising edge on the CNVSTR input signal (pin P0.6)
A Timer 3 overflow
Rev. 1.1
Section “19. Timers” on page 217
Section “14. Port Input/Output” on
for timer configuration.
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