COP8SCE9IMT9 National Semiconductor, COP8SCE9IMT9 Datasheet - Page 11
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COP8SCE9IMT9
Manufacturer Part Number
COP8SCE9IMT9
Description
IC MCU EEPROM 8BIT 8K 48-TSSOP
Manufacturer
National Semiconductor
Series
COP8™ 8Sr
Datasheet
1.COP8SDE9IMT9NOPB.pdf
(70 pages)
Specifications of COP8SCE9IMT9
Core Processor
COP8
Core Size
8-Bit
Speed
20MHz
Connectivity
Microwire/Plus (SPI), UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SCE9IMT9
RAM Retention Voltage, V
Input Capacitance
Voltage on G6 to Force Execution from Boot
ROM(Note 8)
G6 Rise Time to Force Execution from Boot ROM
Input Current on G6 when Input
Instruction Cycle Time (t
Output Propagation Delay
Frequency of MICROWIRE/PLUS in Slave
Mode
MICROWIRE/PLUS Setup Time (t
MICROWIRE/PLUS Hold Time (t
MICROWIRE/PLUS Output Propagation Delay
(t
Input Pulse Width
Output Pulse Width
USART Bit Time when using External CKX
USART CKX Frequency when being Driven by
Internal Baud Rate Generator
Reset Pulse Width
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
t
Note 9: Maximum rate of voltage change must be
Note 10: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 11: The HALT mode will stop CKI from oscillating. Measurement of I
G0, and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to V
clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 12: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
when biased at voltages
must be limited to
Note 13: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 t
Note 14: Absolute Maximum Ratings should not be exceeded.
Note 15: V
UPD
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
C
Crystal/Resonator
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Timer 2, 3 Input High Time (Note 6)
Timer 2, 3 Input Low Time (Note 6)
Timer 2, 3 Output High Time
Timer 2, 3 Output Low Time
= instruction cycle time.
)
cc
must be valid and stable before G6 is raised to a high voltage.
<
(V
Parameter
CC
Parameter
>
+ 7V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
V
CC
C
R
)
(the pins do not have source current when biased at a voltage below V
(in HALT Mode)
DC Electrical Characteristics (−40˚C
>
UWH
UWS
V
CC
)
AC Electrical Characteristics (−40˚C
)
<
0.5 V/ms.
4.5V
R
L
=2.2k, C
G6 rise time must be slower
than 100 ns
V
IN
V
= 11V, V
Conditions
CC
DD
L
HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F,
Conditions
11
= 100 pF
5.5V
CC
= 5.5V
T
A
+125˚C) (Continued)
T
A
CC
periods
6 CKI
). These two pins will not latch up. The voltage at the pins
+125˚C)
Min
150
150
0.5
0.5
20
20
1
1
1
1
1
1
2 x V
>
Min
100
2.0
V
CC
CC
Typ
and the pins will have sink current to V
Typ
500
C
Max
150
.
DC
2
2
V
CC
Max
CC
7
; A/D converter and
+ 7
MCLK or t
MCLK or t
www.national.com
Units
MHz
MHz
µs
ns
ns
ns
ns
ns
t
t
t
t
t
C
C
C
C
C
Units
pF
nS
µA
V
V
C
C
CC
CC