COP8SCR9IMT7 National Semiconductor, COP8SCR9IMT7 Datasheet - Page 45

• Manufacturer Part Number: COP8SCR9IMT7
• Description: IC MCU EEPROM 8BIT 32K 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Sr

Specifications of COP8SCR9IMT7

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: *COP8SCR9IMT7

14.0 USART
14.1 USART CONTROL AND STATUS REGISTERS
The operation of the USART is programmed through three
registers: ENU, ENUR and ENUI.
14.2 DESCRIPTION OF USART REGISTER BITS
ENU — USART CONTROL AND STATUS REGISTER (Ad-
dress at 0BA)
PEN: This bit enables/disables Parity (7- and 8-bit modes
only). Read/Write, cleared on reset.
Bit 7
PEN
PSEL1 XBIT9/
PSEL0
(Continued)
CHL1
CHL0
ERR
FIGURE 22. USART Block Diagram
RBFL
TBMT
Bit 0
45
PEN = 0
PEN = 1
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on
reset.
PSEL1 = 0, PSEL0 = 0
PSEL1 = 0, PSEL1 = 1
PSEL1 = 1, PSEL0 = 0
PSEL1 = 1, PSEL1 = 1
XBIT9/PSEL0: Programs the ninth bit for transmission when
the USART is operating with nine data bits per frame. For
seven or eight data bits per frame, this bit in conjunction with
PSEL1 selects parity. Read/Write, cleared on reset.
CHL1, CHL0: These bits select the character frame format.
Parity is not included and is generated/verified by hardware.
Parity disabled.
Parity enabled.
Odd Parity (if Parity enabled)
Even Parity (if Parity enabled)
Mark(1) (if Parity enabled)
Space(0) (if Parity enabled)
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