C8051F023 Silicon Laboratories Inc, C8051F023 Datasheet - Page 259
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C8051F023
Manufacturer Part Number
C8051F023
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F023
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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23.3. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of PCA0.
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
CF
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the Coun-
ter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the CF inter-
rupt service routine. This bit is not automatically cleared by hardware and must be cleared by
software. See “Important Note About the PCA0CN Register” on page 251.
CR: PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.
UNUSED. Read = 0b, Write = don't care.
CCF4: PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF3: PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF2: PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF1: PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF0: PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
R/W
CR
Bit6
Figure 23.10. PCA0CN: PCA Control Register
R/W
Bit5
-
CCF4
R/W
Bit4
CCF3
R/W
Bit3
Rev. 1.4
CCF2
R/W
Bit2
CCF1
C8051F020/1/2/3
R/W
Bit1
(bit addressable)
CCF0
R/W
Bit0
SFR Address:
00000000
Reset Value
0xD8
259