C8051F121 Silicon Laboratories Inc, C8051F121 Datasheet
C8051F121
Manufacturer Part Number
C8051F121
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F121-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F121R
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
12-Bit ADC
-
-
-
-
-
-
8-Bit ADC
-
-
-
-
Two 12-Bit DACs
-
Two Comparators
Internal Voltage Reference
V
On-Chip JTAG Debug & Boundary Scan
-
-
-
-
-
Precision Mixed Signal
DD
MONEN
±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
±1 LSB INL; no missing codes
Programmable throughput up to 500 ksps
8 external inputs
Programmable amplifier gain: 4, 2, 1, 0.5
Can synchronize outputs to timers for jitter-free waveform generation
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
VREFA
XTAL1
XTAL2
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DGND
DGND
DGND
AGND
DAC1
DAC0
Monitor/Brown-out Detector
VREF
CP0+
CP1+
CP0-
CP1-
VDD
VDD
VDD
TCK
TMS
TDO
RST
AV+
TDI
Oscillator
Oscillator
External
Internal
Circuit
CP0
2%
Digital Power
A
M
U
X
Monitor
Analog Power
VDD
CP1
JTAG
Logic
(12-Bit)
(12-Bit)
VREF
DAC1
DAC0
SENSOR
TEMP
Prog
Gain
Boundary Scan
WDT
Debug HW
N/M
PLL
100 MIPS, 128 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCU
100 ksps
(12-Bit)
System
Clock
ADC
Reset
REFADC
Copyright © 2004 by Silicon Laboratories
C
8
0
5
1
o
e
r
16 x 16 Mult/Acc
8
External Data Memory Bus
(2-cycle)
FLASH
SFR Bus
128 kB
XRAM
256 B
RAM
8 kB
Target Buffer
Prefetch
256 Byte
Branch
HW
32
High-Speed 8051 µC Core
-
-
-
Memory
-
-
-
Digital Peripherals
-
-
-
-
-
-
Clock Sources
-
-
-
Supply Voltage: 3.0 to 3.6 V
-
-
64-Pin TQFP
Temperature Range: –40 to +85 °C
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 100 MIPS throughput with 100 MHz system clock
16 x 16 multiply/accumulate engine (2-cycle)
8448 bytes data RAM
128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
External parallel data memory interface
32 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with six capture/compare
modules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using Timer 3 or PCA
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
On-chip programmable PLL: up to 100 MHz
External oscillator: Crystal, RC, C, or Clock
Typical operating current: 50 mA at 100 MHz
Typical stop mode current: 0.4 uA
SPI Bus
0, 1, 2, 4
Latches
UART0
UART1
Timer 3
P0, P1,
SMBus
Timers
P2, P3
PCA
Address Bus
Bus Control
REFADC
Data Bus
VDD
ADC
500 ksps
(8-Bit)
C
T
L
A
d
d
D
a
a
r
t
O
C
R
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
C8051F121
Prog
Gain
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
M
U
X
8:1
DRV
DRV
DRV
DRV
P4
P5
P6
P7
P0.0
P0.7
P1.0/AIN1.0
P1.7/AIN1.7
P2.0
P2.7
P3.0
P3.7
6.15.2004
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C8051F121 Summary of contents
Page 1
... Target Buffer 5 SPI Bus 8 PCA Prefetch 1 HW Timers Timer 3 128 kB C FLASH P0, P1, P2 Latches 256 B RAM XRAM External Data Memory Bus Mult/Acc (2-cycle) Copyright © 2004 by Silicon Laboratories C8051F121 P0.0 P0 Drv P0 P1.0/AIN1 Drv P1.7/AIN1 P2 Drv P2 P3.0 P3 Drv P3.7 REFADC VDD A ADC ...
Page 2
... A1 0.05 - 0.15 A2 0.95 - 1.05 b 0.17 0.22 0. 12. 10. 0. 12. 10.00 - Copyright © 2004 by Silicon Laboratories C8051F121 TYP MAX UNITS 3 0 µA 10 µA 0.4 µA 100 MHz 24.5 25.0 MHz 98 100 MHz 12 bits ±1 LSB ±1 LSB 69 dB 100 ksps 12 bits ± ...