C8051F131 Silicon Laboratories Inc, C8051F131 Datasheet - Page 73

• Manufacturer Part Number: C8051F131
• Description: IC 8051 MCU 128K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F131

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1148

6.
The ADC0 subsystem for the C8051F122/3/6/7 and C8051F13x consists of a 9-channel, configurable ana-
log multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-
approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see
block diagram in Figure 6.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all
configurable under software control via the Special Function Registers shown in Figure 6.1. The voltage
reference used by ADC0 is selected as described in
ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when the AD0EN bit in the ADC0
Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is
logic 0.
6.1.
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-chip temperature sensor (temperature transfer function is shown in Figure 6.2). AMUX
input pairs can be programmed to operate in either differential or single-ended mode. This allows the user
to select the best measurement technique for each input channel, and even accommodates mode
changes "on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are two registers
associated with the AMUX: the Channel Selection register AMX0SL (SFR Definition 6.2), and the Configu-
ration register AMX0CF (SFR Definition 6.1). The table in SFR Definition 6.2 shows AMUX functionality by
channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount deter-
mined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (SFR Definition
6.3). The PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset.
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13x Only)
Analog Multiplexer and PGA
SENSOR
AGND
TEMP
AMX0CF
ADC0GTH
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
+
+
+
+
-
-
-
-
AMUX
(SE or
9-to-1
DIFF)
AMX0SL
ADC0GTL
X
+
-
AV+
AD0EN
AGND
ADC0CF
Rev. 1.4
ADC0LTH
Section “9. Voltage Reference” on page 113
C8051F120/1/2/3/4/5/6/7
ADC
10-Bit
AV+
SAR
ADC0CN
ADC0LTL
C8051F130/1/2/3
Start Conversion
10
20
Comb.
00
01
10
11
10
Logic
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
AD0WINT
. The
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