C8051F047 Silicon Laboratories Inc, C8051F047 Datasheet - Page 228

• Manufacturer Part Number: C8051F047
• Description: IC 8051 MCU 32K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F047

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1159

C8051F040/1/2/3/4/5/6/7
18.1. Bosch CAN Controller Operation
The CAN Controller featured in the C8051F04x family of devices is a full implementation of Bosch’s full
CAN module and fully complies with CAN specification 2.0B. A block diagram of the CAN controller is
shown in Figure 18.2. The CAN Core provides shifting (CANTX and CANRX), serial/parallel conversion of
messages, and other protocol related tasks such as transmission of data and acceptance filtering. The
message RAM stores 32 message objects which can be received or transmitted on a CAN network. The
CAN registers and message handler provide an interface for data transfer and notification between the
CAN controller and the CIP-51.
The function and use of the CAN Controller is detailed in the Bosch CAN User’s Guide. The User’s Guide
should be used as a reference to configure and use the CAN controller. This Silicon Labs data sheet
describes how to access the CAN controller.
The CAN Controller is typically initialized using the following steps:
The CAN Control Register (CAN0CN), CAN Test Register (CAN0TST), and CAN Status Register
(CAN0STA) in the CAN controller can be accessed directly or indirectly via CIP-51 SFR’s. All other CAN
registers must be accessed via an indirect indexing method described in
CAN0ADR, CAN0DATH, and CANDATL to Access CAN Registers” on page
228
Step 1. Set the SFRPAGE register to CAN0_PAGE.
Step 2. Set the INIT the CCE bits to ‘1’ in the CAN0CN Register. See the CAN User’s Guide for bit
Step 3. Set timing parameters in the Bit Timing Register and the BRP Extension Register.
Step 4. Initialize each message object or set it’s MsgVal bit to NOT VALID.
Step 5. Reset the INIT bit to ‘0’.
definitions.
CANTX
TX
(32 Message Objects)
Figure 18.2. CAN Controller Diagram
Message RAM
Core
CAN
Message Handler
CANRX
RX
Rev. 1.5
CAN Controller
REGISTERS
Prescaler
BRP
Interrupt
CAN_CLK
(f
sys
)
C8051F04x
232.
Section “18.2.5. Using
CIP-51
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