SAF-XC164CS-32F20F BB-A Infineon Technologies, SAF-XC164CS-32F20F BB-A Datasheet - Page 50

• Manufacturer Part Number: SAF-XC164CS-32F20F BB-A
• Description: IC MCU 16BIT FLASH TQFP-100-16
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164CS-32F20F BB-A

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Packages: PG-TQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 256.0 KByte
• For Use With: B158-H8962-X-X-7600IN - KIT EASY XC164CSMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: FX164CS32F20FBBANT; FX164CS32F20FBBAXT; SAFXC164CS32F20FBBAT; SP000098787; SP000224590

3.18
Table 8
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 8
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR/BSET
BMOV(N)
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit
BCMP
BFLDH/BFLDL
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL/SHR
Data Sheet
lists the instructions of the XC164CS in a condensed way.
Instruction Set Summary
Instruction Set Summary
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR
(16- × 16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise exclusive OR, (word/byte operands)
Clear/Set direct bit
Move (negated) direct bit to direct bit
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
48
Functional Description
Derivatives
V1.1, 2006-08
XC164-32
Bytes
2 / 4
2 / 4
2 / 4
2 / 4
2
2
2
2 / 4
2 / 4
2 / 4
2
4
4
4
4
2 / 4
2 / 4
2 / 4
2
2