AD8557ARZ Analog Devices Inc, AD8557ARZ Datasheet - Page 17

• Manufacturer Part Number: AD8557ARZ
• Description: IC AMP CHOPPER 2MHZ 55MA 8SOIC
• Manufacturer: Analog Devices Inc
• Series: DigiTrim®r

Specifications of AD8557ARZ

• Amplifier Type: Chopper (Zero-Drift)
• Number Of Circuits: 1
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 18nA
• Voltage - Input Offset: 2µV
• Current - Supply: 1.8mA
• Current - Output / Channel: 55mA
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Input Offset Voltage: 12µV
• Gain Db Min: 28dB
• Bandwidth: 2MHz
• Amplifier Output: Single Ended / Differential
• Cmrr: 112dB
• Supply Voltage Range: 2.7V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Slew Rate: -

Table 10. Timing Specifications
Timing Parameter
t
t
t
Table 11. 38-Bit Serial Word Format
Field No.
0
1
2
3
4
5
A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 μs, the 38-bit serial word transfers
in 2.3 ms. Table 11 summarizes the word format.
Field 0 and Field 5 are the start-of-packet field and end-of-
packet field, respectively. Matching the start-of-packet field with
1000 0000 0001 and the end-of-packet field with 0111 1111
1110 ensures that the serial word is valid and enables decoding
of the other fields.
Field 3 breaks up the data and ensures that no data combination
can inadvertently trigger the start-of-packet and end-of-packet
fields. Field 0 should be written first and Field 5 written last.
Within each field, the MSB must be written first and the LSB
written last. The shift register features power-on reset to mini-
mize the risk of inadvertent programming; power-on reset
occurs when VDD is between 0.7 V and 2.2 V.
w0
w1
ws
Bits
0 to 11
12 to 13
14 to 15
16 to 17
18 to 25
26 to 37
Description
Pulse width for loading 0 into shift register
Pulse width for loading 1 into shift register
Width between pulses
2-bit function
2-bit parameter
8-bit value
Description
12-bit start of packet 1000 0000 0001
2-bit dummy 10
12-bit end of packet 0111 1111 1110
00: change sense current
01: simulate parameter value
10: program parameter value
11: read parameter value
00: second stage gain code
01: first stage gain code
10: output offset code
11: other functions
Parameter 00 (second stage gain code): 3 LSBs used
Parameter 01 (first stage gain code): 7 LSBs used
Parameter 10 (output offset code): all 8 bits used
Parameter 11 (other functions)
Bit 0 (LSB): master fuse
Bit 1: fuse for production test at Analog Devices
Rev. B | Page 17 of 24
Initial State
Initially, all the polysilicon fuses are intact. Each parameter has
the value 0 assigned (see Table 12).
Table 12. Initial State Before Programming
Second Stage Gain Code = 0
First stage gain code = 0
Output offset code = 0
Master fuse = 0
When power is applied to a device, parameter values are taken
either from internal registers, if the master fuse is not blown,
or from the polysilicon fuses, if the master fuse is blown.
Programmed values have no effect until the master fuse is
blown. The internal registers feature power-on reset, so the
unprogrammed devices enter a known state after power-up.
Power-on reset occurs when VDD is between 0.7 V and 2.2 V.
Specification
Between 50 ns and 10 μs
≥50 μs
≥10 μs
Second Stage Gain = 10
First stage gain = 2.8
Output offset = VSS
Master fuse not blown
AD8557